Commit aa9083fa authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge tag 'phy-for-5.3' of... 

Merge tag 'phy-for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy

 into usb-next

phy: for 5.3

  *) Add a new PHY driver for Qualcomm PCIe2 PHY
  *) Add a new PHY driver for Mixel DPHY present in i.MX8
  *) Fix Qualcomm QMP UFS PHY driver from incorrectly reporting that
     PHY enable failed
  *) Fix _BUG_ on Amlogic G12A USB3 + PCIE Combo PHY Driver due to
     calling a sleeping function from invalid context
  *) Fix WARN_ON dump on rcar-gen3-usb2 PHY driver caused due to
     imbalance powered flag
  *) Fix .cocci and sparse warnings

Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>

* tag 'phy-for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy:
  phy: qcom-qmp: Raise qcom_qmp_phy_enable() polling delay
  phy: meson-g12a-usb3-pcie: disable locking for cr_regmap
  phy: Add driver for mixel mipi dphy found on NXP's i.MX8 SoCs
  dt-bindings: phy: Add documentation for mixel dphy
  dt-bindings: phy-pxa-usb: add bindings
  phy: renesas: rcar-gen3-usb2: fix imbalance powered flag
  phy: qcom-qmp: Drop useless msm8998_pciephy_cfg setting
  phy: qcom-qmp: Correct READY_STATUS poll break condition
  phy: ti: am654-serdes: Make serdes_am654_xlate() static
  phy: usb: phy-brcm-usb: Fix platform_no_drv_owner.cocci warnings
  phy: samsung: Use struct_size() in devm_kzalloc()
  phy: qcom: Add Qualcomm PCIe2 PHY driver
  dt-bindings: phy: Add binding for Qualcomm PCIe2 PHY
parents 90fca074 52060264

Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt

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Mixel DSI PHY for i.MX8



The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the

MIPI-DSI IP from Northwest Logic). It represents the physical layer for the

electrical signals for DSI.



Required properties:

- compatible: Must be:

  - "fsl,imx8mq-mipi-dphy"

- clocks: Must contain an entry for each entry in clock-names.

- clock-names: Must contain the following entries:

  - "phy_ref": phandle and specifier referring to the DPHY ref clock

- reg: the register range of the PHY controller

- #phy-cells: number of cells in PHY, as defined in

  Documentation/devicetree/bindings/phy/phy-bindings.txt

  this must be <0>



Optional properties:

- power-domains: phandle to power domain



Example:

	dphy: dphy@30a0030 {

		compatible = "fsl,imx8mq-mipi-dphy";

		clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;

		clock-names = "phy_ref";

		reg = <0x30a00300 0x100>;

		power-domains = <&pd_mipi0>;

		#phy-cells = <0>;

        };

Documentation/devicetree/bindings/phy/phy-pxa-usb.txt

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Marvell PXA USB PHY

-------------------



Required properties:

- compatible: one of: "marvell,mmp2-usb-phy", "marvell,pxa910-usb-phy",

	"marvell,pxa168-usb-phy",

- #phy-cells: must be 0



Example:

	usb-phy: usbphy@d4207000 {

		compatible = "marvell,mmp2-usb-phy";

		reg = <0xd4207000 0x40>;

		#phy-cells = <0>;

		status = "okay";

	};



This document explains the device tree binding. For general

information about PHY subsystem refer to Documentation/phy.txt

Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt

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Qualcomm PCIe2 PHY controller

=============================



The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm

platforms.



Required properties:

 - compatible: compatible list, should be:

	       "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"



 - reg: offset and length of the PHY register set.

 - #phy-cells: must be 0.



 - clocks: a clock-specifier pair for the "pipe" clock



 - vdda-vp-supply: phandle to low voltage regulator

 - vdda-vph-supply: phandle to high voltage regulator



 - resets: reset-specifier pairs for the "phy" and "pipe" resets

 - reset-names: list of resets, should contain:

		"phy" and "pipe"



 - clock-output-names: name of the outgoing clock signal from the PHY PLL

 - #clock-cells: must be 0



Example:

 phy@7786000 {

	compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy";

	reg = <0x07786000 0xb8>;



	clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;

	resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>,

	         <&gcc GCC_PCIE_0_PIPE_ARES>;

	reset-names = "phy", "pipe";



	vdda-vp-supply = <&vreg_l3_1p05>;

	vdda-vph-supply = <&vreg_l5_1p8>;



	clock-output-names = "pcie_0_pipe_clk";

	#clock-cells = <0>;

	#phy-cells = <0>;

 };

drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c

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@@ -188,7 +188,7 @@ static const struct regmap_config phy_g12a_usb3_pcie_cr_regmap_conf = { 
	.reg_read = phy_g12a_usb3_pcie_cr_bus_read,

	.reg_write = phy_g12a_usb3_pcie_cr_bus_write,

	.max_register = 0xffff,

	.fast_io = true,

	.disable_locking = true,

};



static int phy_g12a_usb3_init(struct phy *phy)

drivers/phy/broadcom/phy-brcm-usb.c

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@@ -443,7 +443,6 @@ static struct platform_driver brcm_usb_driver = { 
	.remove		= brcm_usb_phy_remove,

	.driver		= {

		.name	= "brcmstb-usb-phy",

		.owner	= THIS_MODULE,

		.pm = &brcm_usb_phy_pm_ops,

		.of_match_table = brcm_usb_dt_ids,

	},

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