Commit aa584d28 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-renesas-for-v4.17-tag2' of... 

Merge tag 'clk-renesas-for-v4.17-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates from Geert Uytterhoeven:

  - Fix the incorrect display clock on R-Car M3-N,
  - Always use readl()/writel(),
  - Small fixes.

* tag 'clk-renesas-for-v4.17-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: cpg-mssr: Adjust r8a77980 ifdef
  clk: renesas: rcar-gen3: Always use readl()/writel()
  clk: renesas: sh73a0: Always use readl()/writel()
  clk: renesas: rza1: Always use readl()/writel()
  clk: renesas: rcar-gen2: Always use readl()/writel()
  clk: renesas: r8a7740: Always use readl()/writel()
  clk: renesas: r8a73a4: Always use readl()/writel()
  clk: renesas: mstp: Always use readl()/writel()
  clk: renesas: div6: Always use readl()/writel()
  clk: renesas: r8a77965: Replace DU2 clock
parents ce33f284 472f5f39

drivers/clk/renesas/clk-div6.c

+11 −11
Original line number Diff line number Diff line
@@ -53,9 +53,9 @@ static int cpg_div6_clock_enable(struct clk_hw *hw) 
	struct div6_clock *clock = to_div6_clock(hw);

	u32 val;



	val = (clk_readl(clock->reg) & ~(CPG_DIV6_DIV_MASK | CPG_DIV6_CKSTP))

	val = (readl(clock->reg) & ~(CPG_DIV6_DIV_MASK | CPG_DIV6_CKSTP))

	    | CPG_DIV6_DIV(clock->div - 1);

	clk_writel(val, clock->reg);

	writel(val, clock->reg);



	return 0;

}
@@ -65,7 +65,7 @@ static void cpg_div6_clock_disable(struct clk_hw *hw) 
	struct div6_clock *clock = to_div6_clock(hw);

	u32 val;



	val = clk_readl(clock->reg);

	val = readl(clock->reg);

	val |= CPG_DIV6_CKSTP;

	/*

	 * DIV6 clocks require the divisor field to be non-zero when stopping
@@ -75,14 +75,14 @@ static void cpg_div6_clock_disable(struct clk_hw *hw) 
	 */

	if (!(val & CPG_DIV6_DIV_MASK))

		val |= CPG_DIV6_DIV_MASK;

	clk_writel(val, clock->reg);

	writel(val, clock->reg);

}



static int cpg_div6_clock_is_enabled(struct clk_hw *hw)

{

	struct div6_clock *clock = to_div6_clock(hw);



	return !(clk_readl(clock->reg) & CPG_DIV6_CKSTP);

	return !(readl(clock->reg) & CPG_DIV6_CKSTP);

}



static unsigned long cpg_div6_clock_recalc_rate(struct clk_hw *hw,
@@ -122,10 +122,10 @@ static int cpg_div6_clock_set_rate(struct clk_hw *hw, unsigned long rate, 


	clock->div = div;



	val = clk_readl(clock->reg) & ~CPG_DIV6_DIV_MASK;

	val = readl(clock->reg) & ~CPG_DIV6_DIV_MASK;

	/* Only program the new divisor if the clock isn't stopped. */

	if (!(val & CPG_DIV6_CKSTP))

		clk_writel(val | CPG_DIV6_DIV(clock->div - 1), clock->reg);

		writel(val | CPG_DIV6_DIV(clock->div - 1), clock->reg);



	return 0;

}
@@ -139,7 +139,7 @@ static u8 cpg_div6_clock_get_parent(struct clk_hw *hw) 
	if (clock->src_width == 0)

		return 0;



	hw_index = (clk_readl(clock->reg) >> clock->src_shift) &

	hw_index = (readl(clock->reg) >> clock->src_shift) &

		   (BIT(clock->src_width) - 1);

	for (i = 0; i < clk_hw_get_num_parents(hw); i++) {

		if (clock->parents[i] == hw_index)
@@ -163,8 +163,8 @@ static int cpg_div6_clock_set_parent(struct clk_hw *hw, u8 index) 
	mask = ~((BIT(clock->src_width) - 1) << clock->src_shift);

	hw_index = clock->parents[index];



	clk_writel((clk_readl(clock->reg) & mask) |

		(hw_index << clock->src_shift), clock->reg);

	writel((readl(clock->reg) & mask) | (hw_index << clock->src_shift),

	       clock->reg);



	return 0;

}
@@ -241,7 +241,7 @@ struct clk * __init cpg_div6_register(const char *name, 
	 * Read the divisor. Disabling the clock overwrites the divisor, so we

	 * need to cache its value for the enable operation.

	 */

	clock->div = (clk_readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1;

	clock->div = (readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1;



	switch (num_parents) {

	case 1:

drivers/clk/renesas/clk-mstp.c

+2 −2
Original line number Diff line number Diff line
@@ -64,13 +64,13 @@ struct mstp_clock { 
static inline u32 cpg_mstp_read(struct mstp_clock_group *group,

				u32 __iomem *reg)

{

	return group->width_8bit ? readb(reg) : clk_readl(reg);

	return group->width_8bit ? readb(reg) : readl(reg);

}



static inline void cpg_mstp_write(struct mstp_clock_group *group, u32 val,

				  u32 __iomem *reg)

{

	group->width_8bit ? writeb(val, reg) : clk_writel(val, reg);

	group->width_8bit ? writeb(val, reg) : writel(val, reg);

}



static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)

drivers/clk/renesas/clk-r8a73a4.c

+5 −6
Original line number Diff line number Diff line
@@ -71,7 +71,7 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg, 




	if (!strcmp(name, "main")) {

		u32 ckscr = clk_readl(cpg->reg + CPG_CKSCR);

		u32 ckscr = readl(cpg->reg + CPG_CKSCR);



		switch ((ckscr >> 28) & 3) {

		case 0:	/* extal1 */
@@ -95,14 +95,14 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg, 
		 * clock implementation and we currently have no need to change

		 * the multiplier value.

		 */

		u32 value = clk_readl(cpg->reg + CPG_PLL0CR);

		u32 value = readl(cpg->reg + CPG_PLL0CR);



		parent_name = "main";

		mult = ((value >> 24) & 0x7f) + 1;

		if (value & BIT(20))

			div = 2;

	} else if (!strcmp(name, "pll1")) {

		u32 value = clk_readl(cpg->reg + CPG_PLL1CR);

		u32 value = readl(cpg->reg + CPG_PLL1CR);



		parent_name = "main";

		/* XXX: enable bit? */
@@ -125,7 +125,7 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg, 
		default:

			return ERR_PTR(-EINVAL);

		}

		value = clk_readl(cpg->reg + cr);

		value = readl(cpg->reg + cr);

		switch ((value >> 5) & 7) {

		case 0:

			parent_name = "main";
@@ -161,8 +161,7 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg, 
			shift = 0;

		}

		div *= 32;

		mult = 0x20 - ((clk_readl(cpg->reg + CPG_FRQCRC) >> shift)

		       & 0x1f);

		mult = 0x20 - ((readl(cpg->reg + CPG_FRQCRC) >> shift) & 0x1f);

	} else {

		struct div4_clk *c;

drivers/clk/renesas/clk-r8a7740.c

+4 −4
Original line number Diff line number Diff line
@@ -98,20 +98,20 @@ r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg, 
		 * clock implementation and we currently have no need to change

		 * the multiplier value.

		 */

		u32 value = clk_readl(cpg->reg + CPG_FRQCRC);

		u32 value = readl(cpg->reg + CPG_FRQCRC);

		parent_name = "system";

		mult = ((value >> 24) & 0x7f) + 1;

	} else if (!strcmp(name, "pllc1")) {

		u32 value = clk_readl(cpg->reg + CPG_FRQCRA);

		u32 value = readl(cpg->reg + CPG_FRQCRA);

		parent_name = "system";

		mult = ((value >> 24) & 0x7f) + 1;

		div = 2;

	} else if (!strcmp(name, "pllc2")) {

		u32 value = clk_readl(cpg->reg + CPG_PLLC2CR);

		u32 value = readl(cpg->reg + CPG_PLLC2CR);

		parent_name = "system";

		mult = ((value >> 24) & 0x3f) + 1;

	} else if (!strcmp(name, "usb24s")) {

		u32 value = clk_readl(cpg->reg + CPG_USBCKCR);

		u32 value = readl(cpg->reg + CPG_USBCKCR);

		if (value & BIT(7))

			/* extal2 */

			parent_name = of_clk_get_parent_name(np, 1);

drivers/clk/renesas/clk-rcar-gen2.c

+8 −9
Original line number Diff line number Diff line
@@ -62,8 +62,7 @@ static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw, 
	unsigned int mult;

	unsigned int val;



	val = (clk_readl(zclk->reg) & CPG_FRQCRC_ZFC_MASK)

	    >> CPG_FRQCRC_ZFC_SHIFT;

	val = (readl(zclk->reg) & CPG_FRQCRC_ZFC_MASK) >> CPG_FRQCRC_ZFC_SHIFT;

	mult = 32 - val;



	return div_u64((u64)parent_rate * mult, 32);
@@ -95,21 +94,21 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate, 
	mult = div_u64((u64)rate * 32, parent_rate);

	mult = clamp(mult, 1U, 32U);



	if (clk_readl(zclk->kick_reg) & CPG_FRQCRB_KICK)

	if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)

		return -EBUSY;



	val = clk_readl(zclk->reg);

	val = readl(zclk->reg);

	val &= ~CPG_FRQCRC_ZFC_MASK;

	val |= (32 - mult) << CPG_FRQCRC_ZFC_SHIFT;

	clk_writel(val, zclk->reg);

	writel(val, zclk->reg);



	/*

	 * Set KICK bit in FRQCRB to update hardware setting and wait for

	 * clock change completion.

	 */

	kick = clk_readl(zclk->kick_reg);

	kick = readl(zclk->kick_reg);

	kick |= CPG_FRQCRB_KICK;

	clk_writel(kick, zclk->kick_reg);

	writel(kick, zclk->kick_reg);



	/*

	 * Note: There is no HW information about the worst case latency.
@@ -121,7 +120,7 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate, 
	 * "super" safe value.

	 */

	for (i = 1000; i; i--) {

		if (!(clk_readl(zclk->kick_reg) & CPG_FRQCRB_KICK))

		if (!(readl(zclk->kick_reg) & CPG_FRQCRB_KICK))

			return 0;



		cpu_relax();
@@ -332,7 +331,7 @@ rcar_gen2_cpg_register_clock(struct device_node *np, struct rcar_gen2_cpg *cpg, 
			mult = config->pll0_mult;

			div = 3;

		} else {

			u32 value = clk_readl(cpg->reg + CPG_PLL0CR);

			u32 value = readl(cpg->reg + CPG_PLL0CR);

			mult = ((value >> 24) & ((1 << 7) - 1)) + 1;

		}

		parent_name = "main";

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