Commit aa1f06dc authored by Thor Thayer's avatar Thor Thayer Committed by Borislav Petkov
Browse files

EDAC, altera: Make OCRAM ECC dependency check generic 



In preparation for the Arria10 peripheral ECCs, move the OCRAM ECC
dependency check into the general ECC area since this same function can
be used by other memories.

Signed-off-by: default avatarThor Thayer <tthayer@opensource.altera.com>
Cc: devicetree@vger.kernel.org
Cc: dinguyen@opensource.altera.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux@arm.linux.org.uk
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/1459450087-24792-4-git-send-email-tthayer@opensource.altera.com


Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
parent 943ad917

drivers/edac/altera_edac.c

+21 −22
Original line number Original line Diff line number Diff line
@@ -648,6 +648,26 @@ static ssize_t altr_edac_device_trig(struct file *file, 
	return count;

	return count;

}

}





/*

 *  Test for memory's ECC dependencies upon entry because platform specific

 *  startup should have initialized the memory and enabled the ECC.

 *  Can't turn on ECC here because accessing un-initialized memory will

 *  cause CE/UE errors possibly causing an ABORT.

 */

static int altr_check_ecc_deps(struct altr_edac_device_dev *device)

{

	void __iomem  *base = device->base;

	const struct edac_device_prv_data *prv = device->data;



	if (readl(base + prv->ecc_en_ofst) & prv->ecc_enable_mask)

		return 0;



	edac_printk(KERN_ERR, EDAC_DEVICE,

		    "%s: No ECC present or ECC disabled.\n",

		    device->edac_dev_name);

	return -ENODEV;

}



static const struct file_operations altr_edac_device_inject_fops = {

static const struct file_operations altr_edac_device_inject_fops = {

	.open = simple_open,

	.open = simple_open,

	.write = altr_edac_device_trig,

	.write = altr_edac_device_trig,
@@ -853,29 +873,8 @@ static void ocram_free_mem(void *p, size_t size, void *other) 
	gen_pool_free((struct gen_pool *)other, (u32)p, size);

	gen_pool_free((struct gen_pool *)other, (u32)p, size);

}

}





/*

 * altr_ocram_check_deps()

 *	Test for OCRAM cache ECC dependencies upon entry because

 *	platform specific startup should have initialized the

 *	On-Chip RAM memory and enabled the ECC.

 *	Can't turn on ECC here because accessing un-initialized

 *	memory will cause CE/UE errors possibly causing an ABORT.

 */

static int altr_ocram_check_deps(struct altr_edac_device_dev *device)

{

	void __iomem  *base = device->base;

	const struct edac_device_prv_data *prv = device->data;



	if (readl(base + prv->ecc_en_ofst) & prv->ecc_enable_mask)

		return 0;



	edac_printk(KERN_ERR, EDAC_DEVICE,

		    "OCRAM: No ECC present or ECC disabled.\n");

	return -ENODEV;

}



const struct edac_device_prv_data ocramecc_data = {

const struct edac_device_prv_data ocramecc_data = {

	.setup = altr_ocram_check_deps,

	.setup = altr_check_ecc_deps,

	.ce_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_SERR),

	.ce_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_SERR),

	.ue_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_DERR),

	.ue_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_DERR),

	.dbgfs_name = "altr_ocram_trigger",

	.dbgfs_name = "altr_ocram_trigger",

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