Commit a9e61410 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/radeon/kms: add dpm support for SI (v7) 



This adds dpm support for SI asics.  This includes:
- dynamic engine clock scaling
- dynamic memory clock scaling
- dynamic voltage scaling
- dynamic pcie gen1/gen2/gen3 switching
- power containment
- shader power scaling

Set radeon.dpm=1 to enable.

v2: enable hainan support, rebase
v3: guard acpi stuff
v4: fix 64 bit math
v5: fix 64 bit div harder
v6: fix thermal interrupt check noticed by Jerome
v7: attempt fix state enable

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a0ceada6

drivers/gpu/drm/radeon/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -79,7 +79,7 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \ 
	si_blit_shaders.o radeon_prime.o radeon_uvd.o cik.o cik_blit_shaders.o \

	r600_dpm.o rs780_dpm.o rv6xx_dpm.o rv770_dpm.o rv730_dpm.o rv740_dpm.o \

	rv770_smc.o cypress_dpm.o btc_dpm.o sumo_dpm.o sumo_smc.o trinity_dpm.o \

	trinity_smc.o ni_dpm.o

	trinity_smc.o ni_dpm.o si_smc.o si_dpm.o



radeon-$(CONFIG_COMPAT) += radeon_ioc32.o

radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o

drivers/gpu/drm/radeon/atombios.h

+3 −0
Original line number Diff line number Diff line
@@ -7763,6 +7763,9 @@ typedef struct _ATOM_PPLIB_EXTENDEDHEADER 
#define ATOM_PP_PLATFORM_CAP_REGULATOR_HOT 0x00010000               // Enable the 'regulator hot' feature.

#define ATOM_PP_PLATFORM_CAP_BACO          0x00020000               // Does the driver supports BACO state.

#define ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE   0x00040000           // Does the driver supports new CAC voltage table.

#define ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY   0x00080000     // Does the driver supports revert GPIO5 polarity.

#define ATOM_PP_PLATFORM_CAP_OUTPUT_THERMAL2GPIO17   0x00100000     // Does the driver supports thermal2GPIO17.

#define ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE   0x00200000   // Does the driver supports VR HOT GPIO Configurable.



typedef struct _ATOM_PPLIB_POWERPLAYTABLE

{

drivers/gpu/drm/radeon/ni_dpm.c

+13 −9
Original line number Diff line number Diff line
@@ -719,7 +719,7 @@ static const u32 cayman_sysls_enable[] = 
struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);

struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);



static struct ni_power_info *ni_get_pi(struct radeon_device *rdev)

struct ni_power_info *ni_get_pi(struct radeon_device *rdev)

{

        struct ni_power_info *pi = rdev->pm.dpm.priv;
@@ -1471,7 +1471,7 @@ static int ni_populate_smc_tdp_limits(struct radeon_device *rdev, 
	return 0;

}



static int ni_copy_and_switch_arb_sets(struct radeon_device *rdev,

int ni_copy_and_switch_arb_sets(struct radeon_device *rdev,

				u32 arb_freq_src, u32 arb_freq_dest)

{

	u32 mc_arb_dram_timing;
@@ -3488,7 +3488,7 @@ void ni_dpm_setup_asic(struct radeon_device *rdev) 
	rv770_enable_acpi_pm(rdev);

}



static void ni_update_current_ps(struct radeon_device *rdev,

void ni_update_current_ps(struct radeon_device *rdev,

			  struct radeon_ps *rps)

{

	struct ni_ps *new_ps = ni_get_ps(rps);
@@ -3500,7 +3500,7 @@ static void ni_update_current_ps(struct radeon_device *rdev, 
	eg_pi->current_rps.ps_priv = &ni_pi->current_ps;

}



static void ni_update_requested_ps(struct radeon_device *rdev,

void ni_update_requested_ps(struct radeon_device *rdev,

			    struct radeon_ps *rps)

{

	struct ni_ps *new_ps = ni_get_ps(rps);
@@ -4192,6 +4192,10 @@ void ni_dpm_print_power_state(struct radeon_device *rdev, 
	printk("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);

	for (i = 0; i < ps->performance_level_count; i++) {

		pl = &ps->performance_levels[i];

		if (rdev->family >= CHIP_TAHITI)

			printk("\t\tpower level 0    sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",

			       pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);

		else

			printk("\t\tpower level 0    sclk: %u mclk: %u vddc: %u vddci: %u\n",

			       pl->sclk, pl->mclk, pl->vddc, pl->vddci);

	}

drivers/gpu/drm/radeon/ni_dpm.h

+7 −0
Original line number Diff line number Diff line
@@ -231,4 +231,11 @@ struct ni_power_info { 
#define NISLANDS_DPM2_SQ_RAMP_STI_SIZE                  0x1E

#define NISLANDS_DPM2_SQ_RAMP_LTI_RATIO                 0xF



int ni_copy_and_switch_arb_sets(struct radeon_device *rdev,

				u32 arb_freq_src, u32 arb_freq_dest);

void ni_update_current_ps(struct radeon_device *rdev,

			  struct radeon_ps *rps);

void ni_update_requested_ps(struct radeon_device *rdev,

			    struct radeon_ps *rps);



#endif

drivers/gpu/drm/radeon/ppsmc.h

+13 −0
Original line number Diff line number Diff line
@@ -26,6 +26,9 @@ 
#pragma pack(push, 1)



#define PPSMC_SWSTATE_FLAG_DC                           0x01

#define PPSMC_SWSTATE_FLAG_UVD                          0x02

#define PPSMC_SWSTATE_FLAG_VCE                          0x04

#define PPSMC_SWSTATE_FLAG_PCIE_X1                      0x08



#define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL             0x00

#define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL             0x01
@@ -36,17 +39,22 @@ 
#define PPSMC_SYSTEMFLAG_GDDR5                          0x04

#define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP               0x08

#define PPSMC_SYSTEMFLAG_REGULATOR_HOT                  0x10

#define PPSMC_SYSTEMFLAG_REGULATOR_HOT_ANALOG           0x20

#define PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO        0x40



#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_MASK              0x07

#define PPSMC_EXTRAFLAGS_AC2DC_DONT_WAIT_FOR_VBLANK     0x08

#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTODPMLOWSTATE   0x00

#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTOINITIALSTATE  0x01

#define PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH      0x02



#define PPSMC_DISPLAY_WATERMARK_LOW                     0

#define PPSMC_DISPLAY_WATERMARK_HIGH                    1



#define PPSMC_STATEFLAG_AUTO_PULSE_SKIP    0x01

#define PPSMC_STATEFLAG_POWERBOOST         0x02

#define PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE 0x20

#define PPSMC_STATEFLAG_DEEPSLEEP_BYPASS   0x40



#define PPSMC_Result_OK             ((uint8_t)0x01)

#define PPSMC_Result_Failed         ((uint8_t)0xFF)
@@ -80,9 +88,14 @@ typedef uint8_t PPSMC_Result; 
#define PPSMC_CACLongTermAvgEnable          ((uint8_t)0x6E)

#define PPSMC_CACLongTermAvgDisable         ((uint8_t)0x6F)

#define PPSMC_MSG_CollectCAC_PowerCorreln   ((uint8_t)0x7A)

#define PPSMC_FlushDataCache                ((uint8_t)0x80)

#define PPSMC_MSG_SetEnabledLevels          ((uint8_t)0x82)

#define PPSMC_MSG_SetForcedLevels           ((uint8_t)0x83)

#define PPSMC_MSG_ResetToDefaults           ((uint8_t)0x84)

#define PPSMC_MSG_EnableDTE                 ((uint8_t)0x87)

#define PPSMC_MSG_DisableDTE                ((uint8_t)0x88)

#define PPSMC_MSG_ThrottleOVRDSCLKDS        ((uint8_t)0x96)

#define PPSMC_MSG_CancelThrottleOVRDSCLKDS  ((uint8_t)0x97)



/* TN */

#define PPSMC_MSG_DPM_Config                ((uint32_t) 0x102)

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