Commit a9afc9ea authored by Jonathan Hunter's avatar Jonathan Hunter Committed by Vinod Koul
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dmaengine: tegra210-adma: Don't program FIFO threshold 



The Tegra210 ADMA supports two modes for transferring data to a FIFO
which are ...

1. Transfer data to/from the FIFO as soon as a single burst can be
   transferred.
2. Transfer data to/from the FIFO based upon FIFO thresholds, where
   the FIFO threshold is specified in terms on multiple bursts.

Currently, the ADMA driver programs the FIFO threshold values in the
FIFO_CTRL register, but never enables the transfer mode that uses
these threshold values. Given that these have never been used so far,
simplify the ADMA driver by removing the programming of these threshold
values.

Signed-off-by: default avatarJonathan Hunter <jonathanh@nvidia.com>
Acked-by: default avatarThierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20190731101639.22755-1-jonathanh@nvidia.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 57dbd0e4

drivers/dma/tegra210-adma.c

+2 −10
Original line number Diff line number Diff line
@@ -42,12 +42,8 @@ 
#define ADMA_CH_CONFIG_MAX_BUFS				8



#define ADMA_CH_FIFO_CTRL				0x2c

#define TEGRA210_ADMA_CH_FIFO_CTRL_OFLWTHRES(val)	(((val) & 0xf) << 24)

#define TEGRA210_ADMA_CH_FIFO_CTRL_STRVTHRES(val)	(((val) & 0xf) << 16)

#define TEGRA210_ADMA_CH_FIFO_CTRL_TXSIZE(val)		(((val) & 0xf) << 8)

#define TEGRA210_ADMA_CH_FIFO_CTRL_RXSIZE(val)		((val) & 0xf)

#define TEGRA186_ADMA_CH_FIFO_CTRL_OFLWTHRES(val)	(((val) & 0x1f) << 24)

#define TEGRA186_ADMA_CH_FIFO_CTRL_STRVTHRES(val)	(((val) & 0x1f) << 16)

#define TEGRA186_ADMA_CH_FIFO_CTRL_TXSIZE(val)		(((val) & 0x1f) << 8)

#define TEGRA186_ADMA_CH_FIFO_CTRL_RXSIZE(val)		((val) & 0x1f)
@@ -64,14 +60,10 @@ 


#define TEGRA_ADMA_BURST_COMPLETE_TIME			20



#define TEGRA210_FIFO_CTRL_DEFAULT (TEGRA210_ADMA_CH_FIFO_CTRL_OFLWTHRES(1) | \

				    TEGRA210_ADMA_CH_FIFO_CTRL_STRVTHRES(1) | \

				    TEGRA210_ADMA_CH_FIFO_CTRL_TXSIZE(3)    | \

#define TEGRA210_FIFO_CTRL_DEFAULT (TEGRA210_ADMA_CH_FIFO_CTRL_TXSIZE(3) | \

				    TEGRA210_ADMA_CH_FIFO_CTRL_RXSIZE(3))



#define TEGRA186_FIFO_CTRL_DEFAULT (TEGRA186_ADMA_CH_FIFO_CTRL_OFLWTHRES(1) | \

				    TEGRA186_ADMA_CH_FIFO_CTRL_STRVTHRES(1) | \

				    TEGRA186_ADMA_CH_FIFO_CTRL_TXSIZE(3)    | \

#define TEGRA186_FIFO_CTRL_DEFAULT (TEGRA186_ADMA_CH_FIFO_CTRL_TXSIZE(3) | \

				    TEGRA186_ADMA_CH_FIFO_CTRL_RXSIZE(3))



#define ADMA_CH_REG_FIELD_VAL(val, mask, shift)	(((val) & mask) << shift)

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