Commit a99d744d authored by Sowjanya Komatineni's avatar Sowjanya Komatineni Committed by Thierry Reding
Browse files

clk: tegra: clk-dfll: Add suspend and resume support 



This patch implements DFLL suspend and resume operation.

During system suspend entry, CPU clock will switch CPU to safe
clock source of PLLP and disables DFLL clock output.

DFLL driver suspend confirms DFLL disable state and errors out on
being active.

DFLL is re-initialized during the DFLL driver resume as it goes
through complete reset during suspend entry.

Acked-by: default avatarThierry Reding <treding@nvidia.com>
Reviewed-by: default avatarDmitry Osipenko <digetx@gmail.com>
Signed-off-by: default avatarSowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent f8fd9752

drivers/clk/tegra/clk-dfll.c

+56 −0
Original line number Diff line number Diff line
@@ -1487,6 +1487,7 @@ static int dfll_init(struct tegra_dfll *td) 
	td->last_unrounded_rate = 0;



	pm_runtime_enable(td->dev);

	pm_runtime_irq_safe(td->dev);

	pm_runtime_get_sync(td->dev);



	dfll_set_mode(td, DFLL_DISABLED);
@@ -1513,6 +1514,61 @@ di_err1: 
	return ret;

}



/**

 * tegra_dfll_suspend - check DFLL is disabled

 * @dev: DFLL device *

 *

 * DFLL clock should be disabled by the CPUFreq driver. So, make

 * sure it is disabled and disable all clocks needed by the DFLL.

 */

int tegra_dfll_suspend(struct device *dev)

{

	struct tegra_dfll *td = dev_get_drvdata(dev);



	if (dfll_is_running(td)) {

		dev_err(td->dev, "DFLL still enabled while suspending\n");

		return -EBUSY;

	}



	reset_control_assert(td->dvco_rst);



	return 0;

}

EXPORT_SYMBOL(tegra_dfll_suspend);



/**

 * tegra_dfll_resume - reinitialize DFLL on resume

 * @dev: DFLL instance

 *

 * DFLL is disabled and reset during suspend and resume.

 * So, reinitialize the DFLL IP block back for use.

 * DFLL clock is enabled later in closed loop mode by CPUFreq

 * driver before switching its clock source to DFLL output.

 */

int tegra_dfll_resume(struct device *dev)

{

	struct tegra_dfll *td = dev_get_drvdata(dev);



	reset_control_deassert(td->dvco_rst);



	pm_runtime_get_sync(td->dev);



	dfll_set_mode(td, DFLL_DISABLED);

	dfll_set_default_params(td);



	if (td->soc->init_clock_trimmers)

		td->soc->init_clock_trimmers();



	dfll_set_open_loop_config(td);



	dfll_init_out_if(td);



	pm_runtime_put_sync(td->dev);



	return 0;

}

EXPORT_SYMBOL(tegra_dfll_resume);



/*

 * DT data fetch

 */

drivers/clk/tegra/clk-dfll.h

+2 −0
Original line number Diff line number Diff line
@@ -42,5 +42,7 @@ int tegra_dfll_register(struct platform_device *pdev, 
struct tegra_dfll_soc_data *tegra_dfll_unregister(struct platform_device *pdev);

int tegra_dfll_runtime_suspend(struct device *dev);

int tegra_dfll_runtime_resume(struct device *dev);

int tegra_dfll_suspend(struct device *dev);

int tegra_dfll_resume(struct device *dev);



#endif /* __DRIVERS_CLK_TEGRA_CLK_DFLL_H */

drivers/clk/tegra/clk-tegra124-dfll-fcpu.c

+1 −0
Original line number Diff line number Diff line
@@ -631,6 +631,7 @@ static int tegra124_dfll_fcpu_remove(struct platform_device *pdev) 
static const struct dev_pm_ops tegra124_dfll_pm_ops = {

	SET_RUNTIME_PM_OPS(tegra_dfll_runtime_suspend,

			   tegra_dfll_runtime_resume, NULL)

	SET_SYSTEM_SLEEP_PM_OPS(tegra_dfll_suspend, tegra_dfll_resume)

};



static struct platform_driver tegra124_dfll_fcpu_driver = {

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