Commit a9750a31 authored by Yazen Ghannam's avatar Yazen Ghannam Committed by Ingo Molnar
Browse files

x86/mce: Define vendor-specific MSR accessors 



Scalable MCA processors have a whole new range of MSR addresses to
obtain bank related info such as CTL, MISC, ADDR, STATUS. Therefore, we
need a way to abstract the MSR addresses per vendor.

Carved out from a patch by Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>.

Signed-off-by: default avatarYazen Ghannam <Yazen.Ghannam@amd.com>
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Aravind Gopalakrishnan <aravindksg.lkml@gmail.com>
Cc: Ashok Raj <ashok.raj@intel.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/1462019637-16474-5-git-send-email-bp@alien8.de


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent bb91f8c0

arch/x86/include/asm/mce.h

+15 −0
Original line number Diff line number Diff line
@@ -104,10 +104,16 @@ 
#define MCE_LOG_SIGNATURE	"MACHINECHECK"



/* AMD Scalable MCA */

#define MSR_AMD64_SMCA_MC0_CTL		0xc0002000

#define MSR_AMD64_SMCA_MC0_STATUS	0xc0002001

#define MSR_AMD64_SMCA_MC0_ADDR		0xc0002002

#define MSR_AMD64_SMCA_MC0_MISC0	0xc0002003

#define MSR_AMD64_SMCA_MC0_CONFIG	0xc0002004

#define MSR_AMD64_SMCA_MC0_IPID		0xc0002005

#define MSR_AMD64_SMCA_MC0_MISC1	0xc000200a

#define MSR_AMD64_SMCA_MCx_CTL(x)	(MSR_AMD64_SMCA_MC0_CTL + 0x10*(x))

#define MSR_AMD64_SMCA_MCx_STATUS(x)	(MSR_AMD64_SMCA_MC0_STATUS + 0x10*(x))

#define MSR_AMD64_SMCA_MCx_ADDR(x)	(MSR_AMD64_SMCA_MC0_ADDR + 0x10*(x))

#define MSR_AMD64_SMCA_MCx_MISC(x)	(MSR_AMD64_SMCA_MC0_MISC0 + 0x10*(x))

#define MSR_AMD64_SMCA_MCx_CONFIG(x)	(MSR_AMD64_SMCA_MC0_CONFIG + 0x10*(x))

#define MSR_AMD64_SMCA_MCx_IPID(x)	(MSR_AMD64_SMCA_MC0_IPID + 0x10*(x))
@@ -168,9 +174,18 @@ struct mce_vendor_flags { 


	      __reserved_0	: 61;

};



struct mca_msr_regs {

	u32 (*ctl)	(int bank);

	u32 (*status)	(int bank);

	u32 (*addr)	(int bank);

	u32 (*misc)	(int bank);

};



extern struct mce_vendor_flags mce_flags;



extern struct mca_config mca_cfg;

extern struct mca_msr_regs msr_ops;

extern void mce_register_decode_chain(struct notifier_block *nb);

extern void mce_unregister_decode_chain(struct notifier_block *nb);

arch/x86/kernel/cpu/mcheck/mce.c

+47 −0
Original line number Diff line number Diff line
@@ -224,6 +224,53 @@ void mce_unregister_decode_chain(struct notifier_block *nb) 
}

EXPORT_SYMBOL_GPL(mce_unregister_decode_chain);



static inline u32 ctl_reg(int bank)

{

	return MSR_IA32_MCx_CTL(bank);

}



static inline u32 status_reg(int bank)

{

	return MSR_IA32_MCx_STATUS(bank);

}



static inline u32 addr_reg(int bank)

{

	return MSR_IA32_MCx_ADDR(bank);

}



static inline u32 misc_reg(int bank)

{

	return MSR_IA32_MCx_MISC(bank);

}



static inline u32 smca_ctl_reg(int bank)

{

	return MSR_AMD64_SMCA_MCx_CTL(bank);

}



static inline u32 smca_status_reg(int bank)

{

	return MSR_AMD64_SMCA_MCx_STATUS(bank);

}



static inline u32 smca_addr_reg(int bank)

{

	return MSR_AMD64_SMCA_MCx_ADDR(bank);

}



static inline u32 smca_misc_reg(int bank)

{

	return MSR_AMD64_SMCA_MCx_MISC(bank);

}



struct mca_msr_regs msr_ops = {

	.ctl	= ctl_reg,

	.status	= status_reg,

	.addr	= addr_reg,

	.misc	= misc_reg

};



static void print_mce(struct mce *m)

{

	int ret = 0;

CRA Git | Maintained and supported by SUSTech CRA and CCSE