platform/x86: intel_pmc_ipc: Drop intel_pmc_gcr_read() and intel_pmc_gcr_write() (a97368b3) · Commits · 戴 / test

arch/x86/include/asm/intel_pmc_ipc.h

+0 −12

Original line number	Diff line number	Diff line
		@@ -34,9 +34,7 @@
		int intel_pmc_ipc_command(u32 cmd, u32 sub, u8 *in, u32 inlen,
		u32 *out, u32 outlen);
		int intel_pmc_s0ix_counter_read(u64 *data);
		int intel_pmc_gcr_read(u32 offset, u32 *data);
		int intel_pmc_gcr_read64(u32 offset, u64 *data);
		int intel_pmc_gcr_write(u32 offset, u32 data);

		#else

		@@ -51,21 +49,11 @@ static inline int intel_pmc_s0ix_counter_read(u64 *data)
		return -EINVAL;
		}

		static inline int intel_pmc_gcr_read(u32 offset, u32 *data)
		{
		return -EINVAL;
		}

		static inline int intel_pmc_gcr_read64(u32 offset, u64 *data)
		{
		return -EINVAL;
		}

		static inline int intel_pmc_gcr_write(u32 offset, u32 data)
		{
		return -EINVAL;
		}

		#endif /CONFIG_INTEL_PMC_IPC/

		#endif

drivers/platform/x86/intel_pmc_ipc.c

+0 −59

Original line number	Diff line number	Diff line
		@@ -210,35 +210,6 @@ static inline int is_gcr_valid(u32 offset)
		return 0;
		}

		/**
		* intel_pmc_gcr_read() - Read a 32-bit PMC GCR register
		* @offset: offset of GCR register from GCR address base
		* @data: data pointer for storing the register output
		*
		* Reads the 32-bit PMC GCR register at given offset.
		*
		* Return: negative value on error or 0 on success.
		*/
		int intel_pmc_gcr_read(u32 offset, u32 *data)
		{
		int ret;

		spin_lock(&ipcdev.gcr_lock);

		ret = is_gcr_valid(offset);
		if (ret < 0) {
		spin_unlock(&ipcdev.gcr_lock);
		return ret;
		}

		*data = readl(ipcdev.gcr_mem_base + offset);

		spin_unlock(&ipcdev.gcr_lock);

		return 0;
		}
		EXPORT_SYMBOL_GPL(intel_pmc_gcr_read);

		/**
		* intel_pmc_gcr_read64() - Read a 64-bit PMC GCR register
		* @offset: offset of GCR register from GCR address base
		@@ -268,36 +239,6 @@ int intel_pmc_gcr_read64(u32 offset, u64 *data)
		}
		EXPORT_SYMBOL_GPL(intel_pmc_gcr_read64);

		/**
		* intel_pmc_gcr_write() - Write PMC GCR register
		* @offset: offset of GCR register from GCR address base
		* @data: register update value
		*
		* Writes the PMC GCR register of given offset with given
		* value.
		*
		* Return: negative value on error or 0 on success.
		*/
		int intel_pmc_gcr_write(u32 offset, u32 data)
		{
		int ret;

		spin_lock(&ipcdev.gcr_lock);

		ret = is_gcr_valid(offset);
		if (ret < 0) {
		spin_unlock(&ipcdev.gcr_lock);
		return ret;
		}

		writel(data, ipcdev.gcr_mem_base + offset);

		spin_unlock(&ipcdev.gcr_lock);

		return 0;
		}
		EXPORT_SYMBOL_GPL(intel_pmc_gcr_write);

		/**
		* intel_pmc_gcr_update() - Update PMC GCR register bits
		* @offset: offset of GCR register from GCR address base

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