Commit a94de2e7 authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge tag 'misc-habanalabs-next-2019-07-04' of...

Merge tag 'misc-habanalabs-next-2019-07-04' of git://people.freedesktop.org/~gabbayo/linux into char-misc-next

Oded writes:

This tag contains the following changes for kernel 5.3:

- Change the way the device's CPU access the host memory. This allows the
  driver to use the kernel API of setting DMA mask in a standard way (call
  it once).

- Add a new debugfs entry to show the status of the internal DMA and
  compute engines. This is very helpful for debugging in case a command
  submission get stuck.

- Return to the user a mask of the internal engines indicating their busy
  state.

- Make sure to restore registers that can be modified by the user to their
  default values. Only applies to registers that are initialized by the
  driver.

- Elimination of redundant and dead-code.

- Support memset of the device's memory with size larger then 4GB

- Force the user to set the device to debug mode before configuring the
  device's coresight infrastructure

- Improve error printing in case of interrupts from the device

* tag 'misc-habanalabs-next-2019-07-04' of git://people.freedesktop.org/~gabbayo/linux: (31 commits)
  habanalabs: Add busy engines bitmask to HW idle IOCTL
  habanalabs: Add debugfs node for engines status
  habanalabs: Update the device idle check
  habanalabs: Allow accessing host mapped addresses via debugfs
  habanalabs: add WARN in case of bad MMU mapping
  habanalabs: remove DMA mask hack for Goya
  habanalabs: set Goya CPU to use ASIC MMU
  habanalabs: add MMU mappings for Goya CPU
  habanalabs: initialize MMU context for driver
  habanalabs: de-couple MMU and VM module initialization
  habanalabs: initialize device CPU queues after MMU init
  docs/habanalabs: update text for some entries in sysfs
  habanalabs: add rate-limit to an error message
  habanalabs: remove simulator dedicated code
  habanalabs: restore unsecured registers default values
  habanalabs: clear sobs and monitors in context switch
  habanalabs: make tpc registers secured
  habanalabs: don't limit packet size for device CPU
  habanalabs: support device memory memset > 4GB
  habanalabs: print event name for fatal and non-RAZWI events
  ...
parents 60e8523e e8960ca0
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+15 −3
Original line number Diff line number Diff line
@@ -3,7 +3,10 @@ Date: Jan 2019
KernelVersion:  5.1
Contact:        oded.gabbay@gmail.com
Description:    Sets the device address to be used for read or write through
                PCI bar. The acceptable value is a string that starts with "0x"
                PCI bar, or the device VA of a host mapped memory to be read or
                written directly from the host. The latter option is allowed
                only when the IOMMU is disabled.
                The acceptable value is a string that starts with "0x"

What:           /sys/kernel/debug/habanalabs/hl<n>/command_buffers
Date:           Jan 2019
@@ -33,10 +36,12 @@ Contact: oded.gabbay@gmail.com
Description:    Allows the root user to read or write directly through the
                device's PCI bar. Writing to this file generates a write
                transaction while reading from the file generates a read
                transcation. This custom interface is needed (instead of using
                transaction. This custom interface is needed (instead of using
                the generic Linux user-space PCI mapping) because the DDR bar
                is very small compared to the DDR memory and only the driver can
                move the bar before and after the transaction
                move the bar before and after the transaction.
                If the IOMMU is disabled, it also allows the root user to read
                or write from the host a device VA of a host mapped memory

What:           /sys/kernel/debug/habanalabs/hl<n>/device
Date:           Jan 2019
@@ -46,6 +51,13 @@ Description: Enables the root user to set the device to specific state.
                Valid values are "disable", "enable", "suspend", "resume".
                User can read this property to see the valid values

What:           /sys/kernel/debug/habanalabs/hl<n>/engines
Date:           Jul 2019
KernelVersion:  5.3
Contact:        oded.gabbay@gmail.com
Description:    Displays the status registers values of the device engines and
                their derived idle status

What:           /sys/kernel/debug/habanalabs/hl<n>/i2c_addr
Date:           Jan 2019
KernelVersion:  5.1
+24 −18
Original line number Diff line number Diff line
@@ -62,18 +62,20 @@ What: /sys/class/habanalabs/hl<n>/ic_clk
Date:           Jan 2019
KernelVersion:  5.1
Contact:        oded.gabbay@gmail.com
Description:    Allows the user to set the maximum clock frequency of the
                Interconnect fabric. Writes to this parameter affect the device
                only when the power management profile is set to "manual" mode.
                The device IC clock might be set to lower value then the
Description:    Allows the user to set the maximum clock frequency, in Hz, of
                the Interconnect fabric. Writes to this parameter affect the
                device only when the power management profile is set to "manual"
                mode. The device IC clock might be set to lower value than the
                maximum. The user should read the ic_clk_curr to see the actual
                frequency value of the IC
                frequency value of the IC. This property is valid only for the
                Goya ASIC family

What:           /sys/class/habanalabs/hl<n>/ic_clk_curr
Date:           Jan 2019
KernelVersion:  5.1
Contact:        oded.gabbay@gmail.com
Description:    Displays the current clock frequency of the Interconnect fabric
Description:    Displays the current clock frequency, in Hz, of the Interconnect
                fabric. This property is valid only for the Goya ASIC family

What:           /sys/class/habanalabs/hl<n>/infineon_ver
Date:           Jan 2019
@@ -92,18 +94,20 @@ What: /sys/class/habanalabs/hl<n>/mme_clk
Date:           Jan 2019
KernelVersion:  5.1
Contact:        oded.gabbay@gmail.com
Description:    Allows the user to set the maximum clock frequency of the
                MME compute engine. Writes to this parameter affect the device
                only when the power management profile is set to "manual" mode.
                The device MME clock might be set to lower value then the
Description:    Allows the user to set the maximum clock frequency, in Hz, of
                the MME compute engine. Writes to this parameter affect the
                device only when the power management profile is set to "manual"
                mode. The device MME clock might be set to lower value than the
                maximum. The user should read the mme_clk_curr to see the actual
                frequency value of the MME
                frequency value of the MME. This property is valid only for the
                Goya ASIC family

What:           /sys/class/habanalabs/hl<n>/mme_clk_curr
Date:           Jan 2019
KernelVersion:  5.1
Contact:        oded.gabbay@gmail.com
Description:    Displays the current clock frequency of the MME compute engine
Description:    Displays the current clock frequency, in Hz, of the MME compute
                engine. This property is valid only for the Goya ASIC family

What:           /sys/class/habanalabs/hl<n>/pci_addr
Date:           Jan 2019
@@ -163,18 +167,20 @@ What: /sys/class/habanalabs/hl<n>/tpc_clk
Date:           Jan 2019
KernelVersion:  5.1
Contact:        oded.gabbay@gmail.com
Description:    Allows the user to set the maximum clock frequency of the
                TPC compute engines. Writes to this parameter affect the device
                only when the power management profile is set to "manual" mode.
                The device TPC clock might be set to lower value then the
Description:    Allows the user to set the maximum clock frequency, in Hz, of
                the TPC compute engines. Writes to this parameter affect the
                device only when the power management profile is set to "manual"
                mode. The device TPC clock might be set to lower value than the
                maximum. The user should read the tpc_clk_curr to see the actual
                frequency value of the TPC
                frequency value of the TPC. This property is valid only for
                Goya ASIC family

What:           /sys/class/habanalabs/hl<n>/tpc_clk_curr
Date:           Jan 2019
KernelVersion:  5.1
Contact:        oded.gabbay@gmail.com
Description:    Displays the current clock frequency of the TPC compute engines
Description:    Displays the current clock frequency, in Hz, of the TPC compute
                engines. This property is valid only for the Goya ASIC family

What:           /sys/class/habanalabs/hl<n>/uboot_ver
Date:           Jan 2019
+1 −1
Original line number Diff line number Diff line
@@ -18,7 +18,7 @@ int hl_asid_init(struct hl_device *hdev)

	mutex_init(&hdev->asid_mutex);

	/* ASID 0 is reserved for KMD */
	/* ASID 0 is reserved for KMD and device CPU */
	set_bit(0, hdev->asid_bitmap);

	return 0;
+4 −6
Original line number Diff line number Diff line
@@ -682,14 +682,12 @@ int hl_cs_ioctl(struct hl_fpriv *hpriv, void *data)
		u32 tmp;

		rc = hl_poll_timeout_memory(hdev,
			(u64) (uintptr_t) &ctx->thread_ctx_switch_wait_token,
			jiffies_to_usecs(hdev->timeout_jiffies),
			&tmp);
			&ctx->thread_ctx_switch_wait_token, tmp, (tmp == 1),
			100, jiffies_to_usecs(hdev->timeout_jiffies));

		if (rc || !tmp) {
		if (rc == -ETIMEDOUT) {
			dev_err(hdev->dev,
				"context switch phase didn't finish in time\n");
			rc = -ETIMEDOUT;
				"context switch phase timeout (%d)\n", tmp);
			goto out;
		}
	}
+10 −1
Original line number Diff line number Diff line
@@ -31,9 +31,13 @@ static void hl_ctx_fini(struct hl_ctx *ctx)
		 * Coresight might be still working by accessing addresses
		 * related to the stopped engines. Hence stop it explicitly.
		 */
		hdev->asic_funcs->halt_coresight(hdev);
		if (hdev->in_debug)
			hl_device_set_debug_mode(hdev, false);

		hl_vm_ctx_fini(ctx);
		hl_asid_free(hdev, ctx->asid);
	} else {
		hl_mmu_ctx_fini(ctx);
	}
}

@@ -117,6 +121,11 @@ int hl_ctx_init(struct hl_device *hdev, struct hl_ctx *ctx, bool is_kernel_ctx)

	if (is_kernel_ctx) {
		ctx->asid = HL_KERNEL_ASID_ID; /* KMD gets ASID 0 */
		rc = hl_mmu_ctx_init(ctx);
		if (rc) {
			dev_err(hdev->dev, "Failed to init mmu ctx module\n");
			goto mem_ctx_err;
		}
	} else {
		ctx->asid = hl_asid_alloc(hdev);
		if (!ctx->asid) {
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