Commit a947e23a authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'x86-urgent-for-linus' of... 

Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip

* 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:
  x86, asm: Clean up desc.h a bit
  x86, amd: Do not enable ARAT feature on AMD processors below family 0x12
  x86: Move do_page_fault()'s error path under unlikely()
  x86, efi: Retain boot service code until after switching to virtual mode
  x86: Remove unnecessary check in detect_ht()
  x86: Reorder mm_context_t to remove x86_64 alignment padding and thus shrink mm_struct
  x86, UV: Clean up uv_tlb.c
  x86, UV: Add support for SGI UV2 hub chip
  x86, cpufeature: Update CPU feature RDRND to RDRAND
parents 08a8b796 9a3865b1

arch/x86/include/asm/cpufeature.h

+1 −1
Original line number Diff line number Diff line
@@ -125,7 +125,7 @@ 
#define X86_FEATURE_OSXSAVE	(4*32+27) /* "" XSAVE enabled in the OS */

#define X86_FEATURE_AVX		(4*32+28) /* Advanced Vector Extensions */

#define X86_FEATURE_F16C	(4*32+29) /* 16-bit fp conversions */

#define X86_FEATURE_RDRND	(4*32+30) /* The RDRAND instruction */

#define X86_FEATURE_RDRAND	(4*32+30) /* The RDRAND instruction */

#define X86_FEATURE_HYPERVISOR	(4*32+31) /* Running on a hypervisor */



/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */

arch/x86/include/asm/desc.h

+76 −76
Original line number Diff line number Diff line
@@ -4,17 +4,19 @@ 
#include <asm/desc_defs.h>

#include <asm/ldt.h>

#include <asm/mmu.h>



#include <linux/smp.h>



static inline void fill_ldt(struct desc_struct *desc,

			    const struct user_desc *info)

static inline void fill_ldt(struct desc_struct *desc, const struct user_desc *info)

{

	desc->limit0		= info->limit & 0x0ffff;

	desc->base0 = info->base_addr & 0x0000ffff;



	desc->base0		= (info->base_addr & 0x0000ffff);

	desc->base1		= (info->base_addr & 0x00ff0000) >> 16;



	desc->type		= (info->read_exec_only ^ 1) << 1;

	desc->type	       |= info->contents << 2;



	desc->s			= 1;

	desc->dpl		= 0x3;

	desc->p			= info->seg_not_present ^ 1;
@@ -22,6 +24,7 @@ static inline void fill_ldt(struct desc_struct *desc, 
	desc->avl		= info->useable;

	desc->d			= info->seg_32bit;

	desc->g			= info->limit_in_pages;



	desc->base2		= (info->base_addr & 0xff000000) >> 24;

	/*

	 * Don't allow setting of the lm bit. It is useless anyway
@@ -36,6 +39,7 @@ extern gate_desc idt_table[]; 
struct gdt_page {

	struct desc_struct gdt[GDT_ENTRIES];

} __attribute__((aligned(PAGE_SIZE)));



DECLARE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page);



static inline struct desc_struct *get_cpu_gdt_table(unsigned int cpu)
@@ -66,8 +70,7 @@ static inline void pack_gate(gate_desc *gate, unsigned char type, 
			     unsigned short seg)

{

	gate->a = (seg << 16) | (base & 0xffff);

	gate->b = (base & 0xffff0000) |

		  (((0x80 | type | (dpl << 5)) & 0xff) << 8);

	gate->b = (base & 0xffff0000) | (((0x80 | type | (dpl << 5)) & 0xff) << 8);

}



#endif
@@ -75,6 +78,7 @@ static inline void pack_gate(gate_desc *gate, unsigned char type, 
static inline int desc_empty(const void *ptr)

{

	const u32 *desc = ptr;



	return !(desc[0] | desc[1]);

}
@@ -94,12 +98,9 @@ static inline int desc_empty(const void *ptr) 
#define load_TLS(t, cpu)			native_load_tls(t, cpu)

#define set_ldt					native_set_ldt



#define write_ldt_entry(dt, entry, desc)	\

	native_write_ldt_entry(dt, entry, desc)

#define write_gdt_entry(dt, entry, desc, type)		\

	native_write_gdt_entry(dt, entry, desc, type)

#define write_idt_entry(dt, entry, g)		\

	native_write_idt_entry(dt, entry, g)

#define write_ldt_entry(dt, entry, desc)	native_write_ldt_entry(dt, entry, desc)

#define write_gdt_entry(dt, entry, desc, type)	native_write_gdt_entry(dt, entry, desc, type)

#define write_idt_entry(dt, entry, g)		native_write_idt_entry(dt, entry, g)



static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries)

{
@@ -112,33 +113,27 @@ static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries) 


#define store_ldt(ldt) asm("sldt %0" : "=m"(ldt))



static inline void native_write_idt_entry(gate_desc *idt, int entry,

					  const gate_desc *gate)

static inline void native_write_idt_entry(gate_desc *idt, int entry, const gate_desc *gate)

{

	memcpy(&idt[entry], gate, sizeof(*gate));

}



static inline void native_write_ldt_entry(struct desc_struct *ldt, int entry,

					  const void *desc)

static inline void native_write_ldt_entry(struct desc_struct *ldt, int entry, const void *desc)

{

	memcpy(&ldt[entry], desc, 8);

}



static inline void native_write_gdt_entry(struct desc_struct *gdt, int entry,

					  const void *desc, int type)

static inline void

native_write_gdt_entry(struct desc_struct *gdt, int entry, const void *desc, int type)

{

	unsigned int size;



	switch (type) {

	case DESC_TSS:

		size = sizeof(tss_desc);

		break;

	case DESC_LDT:

		size = sizeof(ldt_desc);

		break;

	default:

		size = sizeof(struct desc_struct);

		break;

	case DESC_TSS:	size = sizeof(tss_desc);	break;

	case DESC_LDT:	size = sizeof(ldt_desc);	break;

	default:	size = sizeof(*gdt);		break;

	}



	memcpy(&gdt[entry], desc, size);

}
@@ -154,12 +149,13 @@ static inline void pack_descriptor(struct desc_struct *desc, unsigned long base, 
}





static inline void set_tssldt_descriptor(void *d, unsigned long addr,

					 unsigned type, unsigned size)

static inline void set_tssldt_descriptor(void *d, unsigned long addr, unsigned type, unsigned size)

{

#ifdef CONFIG_X86_64

	struct ldttss_desc64 *desc = d;



	memset(desc, 0, sizeof(*desc));



	desc->limit0		= size & 0xFFFF;

	desc->base0		= PTR_LOW(addr);

	desc->base1		= PTR_MIDDLE(addr) & 0xFF;
@@ -237,14 +233,16 @@ static inline void native_store_idt(struct desc_ptr *dtr) 
static inline unsigned long native_store_tr(void)

{

	unsigned long tr;



	asm volatile("str %0":"=r" (tr));



	return tr;

}



static inline void native_load_tls(struct thread_struct *t, unsigned int cpu)

{

	unsigned int i;

	struct desc_struct *gdt = get_cpu_gdt_table(cpu);

	unsigned int i;



	for (i = 0; i < GDT_ENTRY_TLS_ENTRIES; i++)

		gdt[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i];
@@ -313,6 +311,7 @@ static inline void _set_gate(int gate, unsigned type, void *addr, 
			     unsigned dpl, unsigned ist, unsigned seg)

{

	gate_desc s;



	pack_gate(&s, type, (unsigned long)addr, dpl, ist, seg);

	/*

	 * does not need to be atomic because it is only done once at
@@ -343,9 +342,10 @@ static inline void alloc_system_vector(int vector) 
		set_bit(vector, used_vectors);

		if (first_system_vector > vector)

			first_system_vector = vector;

	} else

	} else {

		BUG();

	}

}



static inline void alloc_intr_gate(unsigned int n, void *addr)

{

arch/x86/include/asm/mmu.h

+2 −2
Original line number Diff line number Diff line
@@ -11,14 +11,14 @@ 
typedef struct {

	void *ldt;

	int size;

	struct mutex lock;

	void *vdso;



#ifdef CONFIG_X86_64

	/* True if mm supports a task running in 32 bit compatibility mode. */

	unsigned short ia32_compat;

#endif



	struct mutex lock;

	void *vdso;

} mm_context_t;



#ifdef CONFIG_SMP

arch/x86/include/asm/uv/uv_bau.h

+386 −204

File changed.

Preview size limit exceeded, changes collapsed.

arch/x86/include/asm/uv/uv_hub.h

+58 −13
Original line number Diff line number Diff line
@@ -77,8 +77,9 @@ 
 *

 *		1111110000000000

 *		5432109876543210

 *		pppppppppplc0cch	Nehalem-EX

 *		ppppppppplcc0cch	Westmere-EX

 *		pppppppppplc0cch	Nehalem-EX (12 bits in hdw reg)

 *		ppppppppplcc0cch	Westmere-EX (12 bits in hdw reg)

 *		pppppppppppcccch	SandyBridge (15 bits in hdw reg)

 *		sssssssssss

 *

 *			p  = pnode bits
@@ -87,7 +88,7 @@ 
 *			h  = hyperthread

 *			s  = bits that are in the SOCKET_ID CSR

 *

 *	Note: Processor only supports 12 bits in the APICID register. The ACPI

 *	Note: Processor may support fewer bits in the APICID register. The ACPI

 *	      tables hold all 16 bits. Software needs to be aware of this.

 *

 *	      Unless otherwise specified, all references to APICID refer to
@@ -138,6 +139,8 @@ struct uv_hub_info_s { 
	unsigned long		global_mmr_base;

	unsigned long		gpa_mask;

	unsigned int		gnode_extra;

	unsigned char		hub_revision;

	unsigned char		apic_pnode_shift;

	unsigned long		gnode_upper;

	unsigned long		lowmem_remap_top;

	unsigned long		lowmem_remap_base;
@@ -149,13 +152,31 @@ struct uv_hub_info_s { 
	unsigned char		m_val;

	unsigned char		n_val;

	struct uv_scir_s	scir;

	unsigned char		apic_pnode_shift;

};



DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);

#define uv_hub_info		(&__get_cpu_var(__uv_hub_info))

#define uv_cpu_hub_info(cpu)	(&per_cpu(__uv_hub_info, cpu))



/*

 * Hub revisions less than UV2_HUB_REVISION_BASE are UV1 hubs. All UV2

 * hubs have revision numbers greater than or equal to UV2_HUB_REVISION_BASE.

 * This is a software convention - NOT the hardware revision numbers in

 * the hub chip.

 */

#define UV1_HUB_REVISION_BASE		1

#define UV2_HUB_REVISION_BASE		3



static inline int is_uv1_hub(void)

{

	return uv_hub_info->hub_revision < UV2_HUB_REVISION_BASE;

}



static inline int is_uv2_hub(void)

{

	return uv_hub_info->hub_revision >= UV2_HUB_REVISION_BASE;

}



union uvh_apicid {

    unsigned long       v;

    struct uvh_apicid_s {
@@ -180,11 +201,25 @@ union uvh_apicid { 
#define UV_PNODE_TO_GNODE(p)		((p) |uv_hub_info->gnode_extra)

#define UV_PNODE_TO_NASID(p)		(UV_PNODE_TO_GNODE(p) << 1)



#define UV_LOCAL_MMR_BASE		0xf4000000UL

#define UV_GLOBAL_MMR32_BASE		0xf8000000UL

#define UV1_LOCAL_MMR_BASE		0xf4000000UL

#define UV1_GLOBAL_MMR32_BASE		0xf8000000UL

#define UV1_LOCAL_MMR_SIZE		(64UL * 1024 * 1024)

#define UV1_GLOBAL_MMR32_SIZE		(64UL * 1024 * 1024)



#define UV2_LOCAL_MMR_BASE		0xfa000000UL

#define UV2_GLOBAL_MMR32_BASE		0xfc000000UL

#define UV2_LOCAL_MMR_SIZE		(32UL * 1024 * 1024)

#define UV2_GLOBAL_MMR32_SIZE		(32UL * 1024 * 1024)



#define UV_LOCAL_MMR_BASE		(is_uv1_hub() ? UV1_LOCAL_MMR_BASE     \

						: UV2_LOCAL_MMR_BASE)

#define UV_GLOBAL_MMR32_BASE		(is_uv1_hub() ? UV1_GLOBAL_MMR32_BASE  \

						: UV2_GLOBAL_MMR32_BASE)

#define UV_LOCAL_MMR_SIZE		(is_uv1_hub() ? UV1_LOCAL_MMR_SIZE :   \

						UV2_LOCAL_MMR_SIZE)

#define UV_GLOBAL_MMR32_SIZE		(is_uv1_hub() ? UV1_GLOBAL_MMR32_SIZE :\

						UV2_GLOBAL_MMR32_SIZE)

#define UV_GLOBAL_MMR64_BASE		(uv_hub_info->global_mmr_base)

#define UV_LOCAL_MMR_SIZE		(64UL * 1024 * 1024)

#define UV_GLOBAL_MMR32_SIZE		(64UL * 1024 * 1024)



#define UV_GLOBAL_GRU_MMR_BASE		0x4000000
@@ -300,6 +335,17 @@ static inline int uv_apicid_to_pnode(int apicid) 
	return (apicid >> uv_hub_info->apic_pnode_shift);

}



/*

 * Convert an apicid to the socket number on the blade

 */

static inline int uv_apicid_to_socket(int apicid)

{

	if (is_uv1_hub())

		return (apicid >> (uv_hub_info->apic_pnode_shift - 1)) & 1;

	else

		return 0;

}



/*

 * Access global MMRs using the low memory MMR32 space. This region supports

 * faster MMR access but not all MMRs are accessible in this space.
@@ -519,14 +565,13 @@ static inline void uv_hub_send_ipi(int pnode, int apicid, int vector) 


/*

 * Get the minimum revision number of the hub chips within the partition.

 *     1 - initial rev 1.0 silicon

 *     2 - rev 2.0 production silicon

 *     1 - UV1 rev 1.0 initial silicon

 *     2 - UV1 rev 2.0 production silicon

 *     3 - UV2 rev 1.0 initial silicon

 */

static inline int uv_get_min_hub_revision_id(void)

{

	extern int uv_min_hub_revision_id;



	return uv_min_hub_revision_id;

	return uv_hub_info->hub_revision;

}



#endif /* CONFIG_X86_64 */

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