MIPS: cmpxchg: Omit redundant barriers for Loongson3 (a91f2a1d) · Commits · 戴 / test

When building a kernel configured to support Loongson3 LL/SC workarounds (ie. CONFIG_CPU_LOONGSON3_WORKAROUNDS=y) the inline assembly in __xchg_asm() & __cmpxchg_asm() already emits completion barriers, and as such we don't need to emit extra barriers from the xchg() or cmpxchg() macros. Add compile-time constant checks causing us to omit the redundant memory barriers. Signed-off-by:

Paul Burton <paul.burton@mips.com> Cc: linux-mips@vger.kernel.org Cc: Huacai Chen <chenhc@lemote.com> Cc: Jiaxun Yang <jiaxun.yang@flygoat.com> Cc: linux-kernel@vger.kernel.org

arch/mips/include/asm/cmpxchg.h

+23 −3

Original line number	Diff line number	Diff line
		@@ -94,6 +94,12 @@ static inline unsigned long __xchg(volatile void *ptr, unsigned long x,
		({ \
		__typeof__(*(ptr)) __res; \
		\
		/* \
		* In the Loongson3 workaround case __xchg_asm() already \
		* contains a completion barrier prior to the LL, so we don't \
		* need to emit an extra one here. \
		*/ \
		if (!__SYNC_loongson3_war) \
		smp_mb__before_llsc(); \
		\
		__res = (__typeof__(*(ptr))) \
		@@ -179,8 +185,22 @@ static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
		({ \
		__typeof__(*(ptr)) __res; \
		\
		/* \
		* In the Loongson3 workaround case __cmpxchg_asm() already \
		* contains a completion barrier prior to the LL, so we don't \
		* need to emit an extra one here. \
		*/ \
		if (!__SYNC_loongson3_war) \
		smp_mb__before_llsc(); \
		\
		__res = cmpxchg_local((ptr), (old), (new)); \
		\
		/* \
		* In the Loongson3 workaround case __cmpxchg_asm() already \
		* contains a completion barrier after the SC, so we don't \
		* need to emit an extra one here. \
		*/ \
		if (!__SYNC_loongson3_war) \
		smp_llsc_mb(); \
		\
		__res; \

Admin message