Commit a91da668 authored Aug 25, 2020 by Clint Taylor Committed by José Roberto de Souza Aug 26, 2020

drm/i915/gt: Implement WA_1406941453



Enable HW Default flip for small PL.

bspec: 52890
bspec: 53508
bspec: 53273

v2: rebase to drm-tip
v3: move from ctx to gt workarounds. Remove whitelist.
v4: move to rcs WA init

Cc: Matt Atwood <matthew.s.atwood@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200826025724.20944-1-clinton.a.taylor@intel.com

parent 4fcee7be

drivers/gpu/drm/i915/gt/intel_workarounds.c

+7 −0

Original line number	Diff line number	Diff line
		@@ -1725,6 +1725,13 @@ rcs_engine_wa_init(struct intel_engine_cs engine, struct i915_wa_list wal)
		FF_DOP_CLOCK_GATE_DISABLE);
		}

		if (IS_GEN(i915, 12)) {
		/* Wa_1406941453:gen12 */
		wa_masked_en(wal,
		GEN10_SAMPLER_MODE,
		ENABLE_SMALLPL);
		}

		if (IS_GEN(i915, 11)) {
		/* This is not an Wa. Enable for better image quality */
		wa_masked_en(wal,

drivers/gpu/drm/i915/i915_reg.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -9315,6 +9315,7 @@ enum {
		#define GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC (1 << 7)

		#define GEN10_SAMPLER_MODE _MMIO(0xE18C)
		#define ENABLE_SMALLPL REG_BIT(15)
		#define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5)

		/* IVYBRIDGE DPF */

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