Commit a8bcb5e5 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/enumeration' 

  - Work around IDT switch ACS Source Validation erratum (James
    Puthukattukaran)

  - Emit diagnostics for all cases of PCIe Link downtraining (Links
    operating slower than they're capable of) (Alexandru Gagniuc)

  - Skip VFs when configuring Max Payload Size (Myron Stowe)

  - Reduce Root Port Max Payload Size if necessary when hot-adding a device
    below it (Myron Stowe)

* pci/enumeration:
  PCI: Match Root Port's MPS to endpoint's MPSS as necessary
  PCI: Skip MPS logic for Virtual Functions (VFs)
  PCI: Check for PCIe Link downtraining
  PCI: Workaround IDT switch ACS Source Validation erratum
parents 1ca358a8 9f0e8935

drivers/pci/pci.c

+20 −7
Original line number Diff line number Diff line
@@ -5301,14 +5301,16 @@ u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed, 
}



/**

 * pcie_print_link_status - Report the PCI device's link speed and width

 * __pcie_print_link_status - Report the PCI device's link speed and width

 * @dev: PCI device to query

 * @verbose: Print info even when enough bandwidth is available

 *

 * Report the available bandwidth at the device.  If this is less than the

 * device is capable of, report the device's maximum possible bandwidth and

 * the upstream link that limits its performance to less than that.

 * If the available bandwidth at the device is less than the device is

 * capable of, report the device's maximum possible bandwidth and the

 * upstream link that limits its performance.  If @verbose, always print

 * the available bandwidth, even if the device isn't constrained.

 */

void pcie_print_link_status(struct pci_dev *dev)

void __pcie_print_link_status(struct pci_dev *dev, bool verbose)

{

	enum pcie_link_width width, width_cap;

	enum pci_bus_speed speed, speed_cap;
@@ -5318,11 +5320,11 @@ void pcie_print_link_status(struct pci_dev *dev) 
	bw_cap = pcie_bandwidth_capable(dev, &speed_cap, &width_cap);

	bw_avail = pcie_bandwidth_available(dev, &limiting_dev, &speed, &width);



	if (bw_avail >= bw_cap)

	if (bw_avail >= bw_cap && verbose)

		pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth (%s x%d link)\n",

			 bw_cap / 1000, bw_cap % 1000,

			 PCIE_SPEED2STR(speed_cap), width_cap);

	else

	else if (bw_avail < bw_cap)

		pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link)\n",

			 bw_avail / 1000, bw_avail % 1000,

			 PCIE_SPEED2STR(speed), width,
@@ -5330,6 +5332,17 @@ void pcie_print_link_status(struct pci_dev *dev) 
			 bw_cap / 1000, bw_cap % 1000,

			 PCIE_SPEED2STR(speed_cap), width_cap);

}



/**

 * pcie_print_link_status - Report the PCI device's link speed and width

 * @dev: PCI device to query

 *

 * Report the available bandwidth at the device.

 */

void pcie_print_link_status(struct pci_dev *dev)

{

	__pcie_print_link_status(dev, true);

}

EXPORT_SYMBOL(pcie_print_link_status);



/**

drivers/pci/pci.h

+5 −0
Original line number Diff line number Diff line
@@ -225,6 +225,10 @@ enum pci_bar_type { 
int pci_configure_extended_tags(struct pci_dev *dev, void *ign);

bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,

				int crs_timeout);

bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,

					int crs_timeout);

int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout);



int pci_setup_device(struct pci_dev *dev);

int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,

		    struct resource *res, unsigned int reg);
@@ -259,6 +263,7 @@ enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); 
enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);

u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,

			   enum pcie_link_width *width);

void __pcie_print_link_status(struct pci_dev *dev, bool verbose);



/* Single Root I/O Virtualization */

struct pci_sriov {

drivers/pci/probe.c

+55 −4
Original line number Diff line number Diff line
@@ -1724,11 +1724,15 @@ int pci_setup_device(struct pci_dev *dev) 
static void pci_configure_mps(struct pci_dev *dev)

{

	struct pci_dev *bridge = pci_upstream_bridge(dev);

	int mps, p_mps, rc;

	int mps, mpss, p_mps, rc;



	if (!pci_is_pcie(dev) || !bridge || !pci_is_pcie(bridge))

		return;



	/* MPS and MRRS fields are of type 'RsvdP' for VFs, short-circuit out */

	if (dev->is_virtfn)

		return;



	mps = pcie_get_mps(dev);

	p_mps = pcie_get_mps(bridge);
@@ -1748,6 +1752,14 @@ static void pci_configure_mps(struct pci_dev *dev) 
	if (pcie_bus_config != PCIE_BUS_DEFAULT)

		return;



	mpss = 128 << dev->pcie_mpss;

	if (mpss < p_mps && pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) {

		pcie_set_mps(bridge, mpss);

		pci_info(dev, "Upstream bridge's Max Payload Size set to %d (was %d, max %d)\n",

			 mpss, p_mps, 128 << bridge->pcie_mpss);

		p_mps = pcie_get_mps(bridge);

	}



	rc = pcie_set_mps(dev, p_mps);

	if (rc) {

		pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
@@ -1756,7 +1768,7 @@ static void pci_configure_mps(struct pci_dev *dev) 
	}



	pci_info(dev, "Max Payload Size set to %d (was %d, max %d)\n",

		 p_mps, mps, 128 << dev->pcie_mpss);

		 p_mps, mps, mpss);

}



static struct hpp_type0 pci_default_type0 = {
@@ -2156,7 +2168,7 @@ static bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 *l, 
	return true;

}



bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,

bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,

					int timeout)

{

	if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
@@ -2172,6 +2184,24 @@ bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l, 


	return true;

}



bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,

				int timeout)

{

#ifdef CONFIG_PCI_QUIRKS

	struct pci_dev *bridge = bus->self;



	/*

	 * Certain IDT switches have an issue where they improperly trigger

	 * ACS Source Validation errors on completions for config reads.

	 */

	if (bridge && bridge->vendor == PCI_VENDOR_ID_IDT &&

	    bridge->device == 0x80b5)

		return pci_idt_bus_quirk(bus, devfn, l, timeout);

#endif



	return pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout);

}

EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);



/*
@@ -2205,6 +2235,25 @@ static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn) 
	return dev;

}



static void pcie_report_downtraining(struct pci_dev *dev)

{

	if (!pci_is_pcie(dev))

		return;



	/* Look from the device up to avoid downstream ports with no devices */

	if ((pci_pcie_type(dev) != PCI_EXP_TYPE_ENDPOINT) &&

	    (pci_pcie_type(dev) != PCI_EXP_TYPE_LEG_END) &&

	    (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM))

		return;



	/* Multi-function PCIe devices share the same link/status */

	if (PCI_FUNC(dev->devfn) != 0 || dev->is_virtfn)

		return;



	/* Print link status only if the device is constrained by the fabric */

	__pcie_print_link_status(dev, false);

}



static void pci_init_capabilities(struct pci_dev *dev)

{

	/* Enhanced Allocation */
@@ -2240,6 +2289,8 @@ static void pci_init_capabilities(struct pci_dev *dev) 
	/* Advanced Error Reporting */

	pci_aer_init(dev);



	pcie_report_downtraining(dev);



	if (pci_probe_reset_function(dev) == 0)

		dev->reset_fn = 1;

}

drivers/pci/quirks.c

+55 −0
Original line number Diff line number Diff line
@@ -4753,3 +4753,58 @@ DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID, 
			      PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);

DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,

			      PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);



/*

 * Some IDT switches incorrectly flag an ACS Source Validation error on

 * completions for config read requests even though PCIe r4.0, sec

 * 6.12.1.1, says that completions are never affected by ACS Source

 * Validation.  Here's the text of IDT 89H32H8G3-YC, erratum #36:

 *

 *   Item #36 - Downstream port applies ACS Source Validation to Completions

 *   Section 6.12.1.1 of the PCI Express Base Specification 3.1 states that

 *   completions are never affected by ACS Source Validation.  However,

 *   completions received by a downstream port of the PCIe switch from a

 *   device that has not yet captured a PCIe bus number are incorrectly

 *   dropped by ACS Source Validation by the switch downstream port.

 *

 * The workaround suggested by IDT is to issue a config write to the

 * downstream device before issuing the first config read.  This allows the

 * downstream device to capture its bus and device numbers (see PCIe r4.0,

 * sec 2.2.9), thus avoiding the ACS error on the completion.

 *

 * However, we don't know when the device is ready to accept the config

 * write, so we do config reads until we receive a non-Config Request Retry

 * Status, then do the config write.

 *

 * To avoid hitting the erratum when doing the config reads, we disable ACS

 * SV around this process.

 */

int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *l, int timeout)

{

	int pos;

	u16 ctrl = 0;

	bool found;

	struct pci_dev *bridge = bus->self;



	pos = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ACS);



	/* Disable ACS SV before initial config reads */

	if (pos) {

		pci_read_config_word(bridge, pos + PCI_ACS_CTRL, &ctrl);

		if (ctrl & PCI_ACS_SV)

			pci_write_config_word(bridge, pos + PCI_ACS_CTRL,

					      ctrl & ~PCI_ACS_SV);

	}



	found = pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout);



	/* Write Vendor ID (read-only) so the endpoint latches its bus/dev */

	if (found)

		pci_bus_write_config_word(bus, devfn, PCI_VENDOR_ID, 0);



	/* Re-enable ACS_SV if it was previously enabled */

	if (ctrl & PCI_ACS_SV)

		pci_write_config_word(bridge, pos + PCI_ACS_CTRL, ctrl);



	return found;

}

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