Commit a8a7cf02 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-next-4.2' of git://people.freedesktop.org/~agd5f/linux into drm-next 

for amdgpu separately next week.  Highlights for radeon:
- VCE1 support
- Bug fixes and misc cleanups

* 'drm-next-4.2' of git://people.freedesktop.org/~agd5f/linux:
  radeon: Deinline indirect register accessor functions
  drm/radeon: Fix max_vblank_count value for current display engines
  drm/radeon: stop using addr to check for BO move
  drm/radeon: clean up radeon_audio_enable
  drm/radeon: take the mode_config mutex when dealing with hpds (v2)
  drm/radeon: make dpcd parameters const
  drm/radeon: Use DECLARE_BITMAP
  drm/radeon/tn/si: enable/disable vce cg when encoding v2
  drm/radeon: add support for vce 1.0 clock gating
  drm/radeon: add VCE 1.0 support v4
  drm/radeon/dpm: add vce support for SI
  drm/radeon/dpm: add vce dpm support for TN
  drm/radeon: implement tn_set_vce_clocks
  drm/radeon: implement si_set_vce_clocks v2
  drm/radeon: allow some more VCE firmware versions
  drm/radeon: rework VCE FW size calculation
  drm/radeon: add a GPU reset counter queryable by userspace
parents c6e7e4bb 9e5acbc2

drivers/gpu/drm/radeon/atombios_dp.c

+4 −4
Original line number Diff line number Diff line
@@ -253,7 +253,7 @@ void radeon_dp_aux_init(struct radeon_connector *radeon_connector) 
#define DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_LEVEL_3

#define DP_PRE_EMPHASIS_MAX    DP_TRAIN_PRE_EMPH_LEVEL_3



static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE],

static void dp_get_adjust_train(const u8 link_status[DP_LINK_STATUS_SIZE],

				int lane_count,

				u8 train_set[4])

{
@@ -311,7 +311,7 @@ static int dp_get_max_dp_pix_clock(int link_rate, 
/***** radeon specific DP functions *****/



int radeon_dp_get_max_link_rate(struct drm_connector *connector,

				u8 dpcd[DP_DPCD_SIZE])

				const u8 dpcd[DP_DPCD_SIZE])

{

	int max_link_rate;
@@ -328,7 +328,7 @@ int radeon_dp_get_max_link_rate(struct drm_connector *connector, 
 * if the max lane# < low rate lane# then use max lane# instead.

 */

static int radeon_dp_get_dp_lane_number(struct drm_connector *connector,

					u8 dpcd[DP_DPCD_SIZE],

					const u8 dpcd[DP_DPCD_SIZE],

					int pix_clock)

{

	int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
@@ -347,7 +347,7 @@ static int radeon_dp_get_dp_lane_number(struct drm_connector *connector, 
}



static int radeon_dp_get_dp_link_clock(struct drm_connector *connector,

				       u8 dpcd[DP_DPCD_SIZE],

				       const u8 dpcd[DP_DPCD_SIZE],

				       int pix_clock)

{

	int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));

drivers/gpu/drm/radeon/cik.c

+25 −0
Original line number Diff line number Diff line
@@ -174,6 +174,31 @@ int cik_get_allowed_info_register(struct radeon_device *rdev, 
	}

}



/*

 * Indirect registers accessor

 */

u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)

{

	unsigned long flags;

	u32 r;



	spin_lock_irqsave(&rdev->didt_idx_lock, flags);

	WREG32(CIK_DIDT_IND_INDEX, (reg));

	r = RREG32(CIK_DIDT_IND_DATA);

	spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);

	return r;

}



void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)

{

	unsigned long flags;



	spin_lock_irqsave(&rdev->didt_idx_lock, flags);

	WREG32(CIK_DIDT_IND_INDEX, (reg));

	WREG32(CIK_DIDT_IND_DATA, (v));

	spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);

}



/* get temperature in millidegrees */

int ci_get_temp(struct radeon_device *rdev)

{

drivers/gpu/drm/radeon/evergreen.c

+69 −0
Original line number Diff line number Diff line
@@ -35,6 +35,75 @@ 
#include "evergreen_blit_shaders.h"

#include "radeon_ucode.h"



/*

 * Indirect registers accessor

 */

u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)

{

	unsigned long flags;

	u32 r;



	spin_lock_irqsave(&rdev->cg_idx_lock, flags);

	WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));

	r = RREG32(EVERGREEN_CG_IND_DATA);

	spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);

	return r;

}



void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)

{

	unsigned long flags;



	spin_lock_irqsave(&rdev->cg_idx_lock, flags);

	WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));

	WREG32(EVERGREEN_CG_IND_DATA, (v));

	spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);

}



u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)

{

	unsigned long flags;

	u32 r;



	spin_lock_irqsave(&rdev->pif_idx_lock, flags);

	WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));

	r = RREG32(EVERGREEN_PIF_PHY0_DATA);

	spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);

	return r;

}



void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)

{

	unsigned long flags;



	spin_lock_irqsave(&rdev->pif_idx_lock, flags);

	WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));

	WREG32(EVERGREEN_PIF_PHY0_DATA, (v));

	spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);

}



u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)

{

	unsigned long flags;

	u32 r;



	spin_lock_irqsave(&rdev->pif_idx_lock, flags);

	WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));

	r = RREG32(EVERGREEN_PIF_PHY1_DATA);

	spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);

	return r;

}



void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)

{

	unsigned long flags;



	spin_lock_irqsave(&rdev->pif_idx_lock, flags);

	WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));

	WREG32(EVERGREEN_PIF_PHY1_DATA, (v));

	spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);

}



static const u32 crtc_offsets[6] =

{

	EVERGREEN_CRTC0_REGISTER_OFFSET,

drivers/gpu/drm/radeon/ni.c

+102 −0
Original line number Diff line number Diff line
@@ -36,6 +36,31 @@ 
#include "radeon_ucode.h"

#include "clearstate_cayman.h"



/*

 * Indirect registers accessor

 */

u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)

{

	unsigned long flags;

	u32 r;



	spin_lock_irqsave(&rdev->smc_idx_lock, flags);

	WREG32(TN_SMC_IND_INDEX_0, (reg));

	r = RREG32(TN_SMC_IND_DATA_0);

	spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);

	return r;

}



void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)

{

	unsigned long flags;



	spin_lock_irqsave(&rdev->smc_idx_lock, flags);

	WREG32(TN_SMC_IND_INDEX_0, (reg));

	WREG32(TN_SMC_IND_DATA_0, (v));

	spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);

}



static const u32 tn_rlc_save_restore_register_list[] =

{

	0x98fc,
@@ -2041,6 +2066,25 @@ static int cayman_startup(struct radeon_device *rdev) 
	if (r)

		rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;



	if (rdev->family == CHIP_ARUBA) {

		r = radeon_vce_resume(rdev);

		if (!r)

			r = vce_v1_0_resume(rdev);



		if (!r)

			r = radeon_fence_driver_start_ring(rdev,

							   TN_RING_TYPE_VCE1_INDEX);

		if (!r)

			r = radeon_fence_driver_start_ring(rdev,

							   TN_RING_TYPE_VCE2_INDEX);



		if (r) {

			dev_err(rdev->dev, "VCE init error (%d).\n", r);

			rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size = 0;

			rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_size = 0;

		}

	}



	r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);

	if (r) {

		dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
@@ -2118,6 +2162,19 @@ static int cayman_startup(struct radeon_device *rdev) 
			DRM_ERROR("radeon: failed initializing UVD (%d).\n", r);

	}



	ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX];

	if (ring->ring_size)

		r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 0x0);



	ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX];

	if (ring->ring_size)

		r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 0x0);



	if (!r)

		r = vce_v1_0_init(rdev);

	else if (r != -ENOENT)

		DRM_ERROR("radeon: failed initializing VCE (%d).\n", r);



	r = radeon_ib_pool_init(rdev);

	if (r) {

		dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
@@ -2273,6 +2330,19 @@ int cayman_init(struct radeon_device *rdev) 
		r600_ring_init(rdev, ring, 4096);

	}



	if (rdev->family == CHIP_ARUBA) {

		r = radeon_vce_init(rdev);

		if (!r) {

			ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX];

			ring->ring_obj = NULL;

			r600_ring_init(rdev, ring, 4096);



			ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX];

			ring->ring_obj = NULL;

			r600_ring_init(rdev, ring, 4096);

		}

	}



	rdev->ih.ring_obj = NULL;

	r600_ih_ring_init(rdev, 64 * 1024);
@@ -2326,6 +2396,7 @@ void cayman_fini(struct radeon_device *rdev) 
	radeon_irq_kms_fini(rdev);

	uvd_v1_0_fini(rdev);

	radeon_uvd_fini(rdev);

	radeon_vce_fini(rdev);

	cayman_pcie_gart_fini(rdev);

	r600_vram_scratch_fini(rdev);

	radeon_gem_fini(rdev);
@@ -2554,3 +2625,34 @@ void cayman_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, 
	radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));

	radeon_ring_write(ring, 0x0);

}



int tn_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk)

{

	struct atom_clock_dividers dividers;

	int r, i;



        r = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,

					   ecclk, false, &dividers);

	if (r)

		return r;



	for (i = 0; i < 100; i++) {

		if (RREG32(CG_ECLK_STATUS) & ECLK_STATUS)

			break;

		mdelay(10);

	}

	if (i == 100)

		return -ETIMEDOUT;



	WREG32_P(CG_ECLK_CNTL, dividers.post_div, ~(ECLK_DIR_CNTL_EN|ECLK_DIVIDER_MASK));



	for (i = 0; i < 100; i++) {

		if (RREG32(CG_ECLK_STATUS) & ECLK_STATUS)

			break;

		mdelay(10);

	}

	if (i == 100)

		return -ETIMEDOUT;



	return 0;

}

drivers/gpu/drm/radeon/nid.h

+7 −0
Original line number Diff line number Diff line
@@ -46,6 +46,13 @@ 


#define DMIF_ADDR_CONFIG  				0xBD4



/* fusion vce clocks */

#define CG_ECLK_CNTL                                    0x620

#       define ECLK_DIVIDER_MASK                        0x7f

#       define ECLK_DIR_CNTL_EN                         (1 << 8)

#define CG_ECLK_STATUS                                  0x624

#       define ECLK_STATUS                              (1 << 0)



/* DCE6 only */

#define DMIF_ADDR_CALC  				0xC00

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