Commit a8856919 authored by Rodrigo Vivi's avatar Rodrigo Vivi
Browse files

Merge tag 'gvt-fixes-2018-02-14' of https://github.com/intel/gvt-linux into drm-intel-fixes 



gvt-fixes-2018-02-14

- gtt mmio 8b access fix (Tina)
- one KBL required mmio reg for switch (Weinan)
- one trace log typo fix (Weinan)

Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180214052827.4nny7vkcoca4vjhn@zhen-hp.sh.intel.com
parents 4b8b41d1 3cc7644e

drivers/gpu/drm/i915/gvt/kvmgt.c

+49 −2
Original line number Diff line number Diff line
@@ -733,6 +733,25 @@ static ssize_t intel_vgpu_rw(struct mdev_device *mdev, char *buf, 
	return ret == 0 ? count : ret;

}



static bool gtt_entry(struct mdev_device *mdev, loff_t *ppos)

{

	struct intel_vgpu *vgpu = mdev_get_drvdata(mdev);

	unsigned int index = VFIO_PCI_OFFSET_TO_INDEX(*ppos);

	struct intel_gvt *gvt = vgpu->gvt;

	int offset;



	/* Only allow MMIO GGTT entry access */

	if (index != PCI_BASE_ADDRESS_0)

		return false;



	offset = (u64)(*ppos & VFIO_PCI_OFFSET_MASK) -

		intel_vgpu_get_bar_gpa(vgpu, PCI_BASE_ADDRESS_0);



	return (offset >= gvt->device_info.gtt_start_offset &&

		offset < gvt->device_info.gtt_start_offset + gvt_ggtt_sz(gvt)) ?

			true : false;

}



static ssize_t intel_vgpu_read(struct mdev_device *mdev, char __user *buf,

			size_t count, loff_t *ppos)

{
@@ -742,7 +761,21 @@ static ssize_t intel_vgpu_read(struct mdev_device *mdev, char __user *buf, 
	while (count) {

		size_t filled;



		if (count >= 4 && !(*ppos % 4)) {

		/* Only support GGTT entry 8 bytes read */

		if (count >= 8 && !(*ppos % 8) &&

			gtt_entry(mdev, ppos)) {

			u64 val;



			ret = intel_vgpu_rw(mdev, (char *)&val, sizeof(val),

					ppos, false);

			if (ret <= 0)

				goto read_err;



			if (copy_to_user(buf, &val, sizeof(val)))

				goto read_err;



			filled = 8;

		} else if (count >= 4 && !(*ppos % 4)) {

			u32 val;



			ret = intel_vgpu_rw(mdev, (char *)&val, sizeof(val),
@@ -802,7 +835,21 @@ static ssize_t intel_vgpu_write(struct mdev_device *mdev, 
	while (count) {

		size_t filled;



		if (count >= 4 && !(*ppos % 4)) {

		/* Only support GGTT entry 8 bytes write */

		if (count >= 8 && !(*ppos % 8) &&

			gtt_entry(mdev, ppos)) {

			u64 val;



			if (copy_from_user(&val, buf, sizeof(val)))

				goto write_err;



			ret = intel_vgpu_rw(mdev, (char *)&val, sizeof(val),

					ppos, true);

			if (ret <= 0)

				goto write_err;



			filled = 8;

		} else if (count >= 4 && !(*ppos % 4)) {

			u32 val;



			if (copy_from_user(&val, buf, sizeof(val)))

drivers/gpu/drm/i915/gvt/mmio_context.c

+1 −0
Original line number Diff line number Diff line
@@ -118,6 +118,7 @@ static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = { 
	{RCS, HALF_SLICE_CHICKEN3, 0xffff, true}, /* 0xe184 */

	{RCS, GEN9_HALF_SLICE_CHICKEN5, 0xffff, true}, /* 0xe188 */

	{RCS, GEN9_HALF_SLICE_CHICKEN7, 0xffff, true}, /* 0xe194 */

	{RCS, GEN8_ROW_CHICKEN, 0xffff, true}, /* 0xe4f0 */

	{RCS, TRVATTL3PTRDW(0), 0, false}, /* 0x4de0 */

	{RCS, TRVATTL3PTRDW(1), 0, false}, /* 0x4de4 */

	{RCS, TRNULLDETCT, 0, false}, /* 0x4de8 */

drivers/gpu/drm/i915/gvt/trace.h

+1 −1
Original line number Diff line number Diff line
@@ -333,7 +333,7 @@ TRACE_EVENT(render_mmio, 
	TP_PROTO(int old_id, int new_id, char *action, unsigned int reg,

		 unsigned int old_val, unsigned int new_val),



	TP_ARGS(old_id, new_id, action, reg, new_val, old_val),

	TP_ARGS(old_id, new_id, action, reg, old_val, new_val),



	TP_STRUCT__entry(

		__field(int, old_id)

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