Commit a85d682a authored by Slava Grigorev's avatar Slava Grigorev Committed by Alex Deucher
Browse files

radeon/audio: consolidate audio_set_dto() functions 



Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarSlava Grigorev <slava.grigorev@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 7991d665

drivers/gpu/drm/radeon/dce3_1_afmt.c

+55 −1
Original line number Diff line number Diff line
@@ -113,6 +113,60 @@ void dce3_2_afmt_write_sad_regs(struct drm_encoder *encoder, 
	}

}



void dce3_2_audio_set_dto(struct radeon_device *rdev,

	struct radeon_crtc *crtc, unsigned int clock)

{

	struct radeon_encoder *radeon_encoder;

	struct radeon_encoder_atom_dig *dig;

	unsigned int max_ratio = clock / 24000;

	u32 dto_phase;

	u32 wallclock_ratio;

	u32 dto_cntl;



	if (!crtc)

		return;



	radeon_encoder = to_radeon_encoder(crtc->encoder);

	dig = radeon_encoder->enc_priv;



	if (!dig)

		return;



	if (max_ratio >= 8) {

		dto_phase = 192 * 1000;

		wallclock_ratio = 3;

	} else if (max_ratio >= 4) {

		dto_phase = 96 * 1000;

		wallclock_ratio = 2;

	} else if (max_ratio >= 2) {

		dto_phase = 48 * 1000;

		wallclock_ratio = 1;

	} else {

		dto_phase = 24 * 1000;

		wallclock_ratio = 0;

	}



	/* Express [24MHz / target pixel clock] as an exact rational

	 * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE

	 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator

	 */

	if (dig->dig_encoder == 0) {

		dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;

		dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);

		WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl);

		WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase);

		WREG32(DCCG_AUDIO_DTO0_MODULE, clock);

		WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */

	} else {

		dto_cntl = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;

		dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);

		WREG32(DCCG_AUDIO_DTO1_CNTL, dto_cntl);

		WREG32(DCCG_AUDIO_DTO1_PHASE, dto_phase);

		WREG32(DCCG_AUDIO_DTO1_MODULE, clock);

		WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */

	}

}



/*

 * update the info frames with the data from the current display mode

 */
@@ -139,7 +193,7 @@ void dce3_1_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *m 
	dig->afmt->pin = radeon_audio_get_pin(encoder);

	radeon_audio_enable(rdev, dig->afmt->pin, 0);



	r600_audio_set_dto(encoder, mode->clock);

	radeon_audio_set_dto(encoder, mode->clock);



	WREG32(HDMI0_VBI_PACKET_CONTROL + offset,

	       HDMI0_NULL_SEND); /* send null packets when required */

drivers/gpu/drm/radeon/dce6_afmt.c

+39 −0
Original line number Diff line number Diff line
@@ -248,3 +248,42 @@ void dce6_audio_enable(struct radeon_device *rdev, 
	WREG32_ENDPOINT(pin->offset, AZ_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,

			enable_mask ? AUDIO_ENABLED : 0);

}



void dce6_hdmi_audio_set_dto(struct radeon_device *rdev,

	struct radeon_crtc *crtc, unsigned int clock)

{

    /* Two dtos; generally use dto0 for HDMI */

	u32 value = 0;



    if (crtc)

		value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);



	WREG32(DCCG_AUDIO_DTO_SOURCE, value);



    /* Express [24MHz / target pixel clock] as an exact rational

     * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE

     * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator

     */

    WREG32(DCCG_AUDIO_DTO0_PHASE, 24000);

    WREG32(DCCG_AUDIO_DTO0_MODULE, clock);

}



void dce6_dp_audio_set_dto(struct radeon_device *rdev,

	struct radeon_crtc *crtc, unsigned int clock)

{

    /* Two dtos; generally use dto1 for DP */

	u32 value = 0;

	value |= DCCG_AUDIO_DTO_SEL;



    if (crtc)

		value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);



	WREG32(DCCG_AUDIO_DTO_SOURCE, value);



    /* Express [24MHz / target pixel clock] as an exact rational

     * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE

     * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator

     */

    WREG32(DCCG_AUDIO_DTO1_PHASE, 24000);

    WREG32(DCCG_AUDIO_DTO1_MODULE, clock);

}

drivers/gpu/drm/radeon/evergreen_hdmi.c

+56 −36
Original line number Diff line number Diff line
@@ -218,26 +218,14 @@ static void evergreen_hdmi_update_avi_infoframe(struct drm_encoder *encoder, 
		frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));

}



static void evergreen_audio_set_dto(struct drm_encoder *encoder, u32 clock)

void dce4_hdmi_audio_set_dto(struct radeon_device *rdev,

	struct radeon_crtc *crtc, unsigned int clock)

{

	struct drm_device *dev = encoder->dev;

	struct radeon_device *rdev = dev->dev_private;

	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);

	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;

	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

	u32 base_rate = 24000;

	u32 max_ratio = clock / base_rate;

	unsigned int max_ratio = clock / 24000;

	u32 dto_phase;

	u32 dto_modulo = clock;

	u32 wallclock_ratio;

	u32 dto_cntl;

	u32 value;



	if (!dig || !dig->afmt)

		return;



	if (ASIC_IS_DCE6(rdev)) {

		dto_phase = 24 * 1000;

	} else {

	if (max_ratio >= 8) {

		dto_phase = 192 * 1000;

		wallclock_ratio = 3;
@@ -251,21 +239,53 @@ static void evergreen_audio_set_dto(struct drm_encoder *encoder, u32 clock) 
		dto_phase = 24 * 1000;

		wallclock_ratio = 0;

	}

		dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;

		dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);

		WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl);

	}



	/* XXX two dtos; generally use dto0 for hdmi */

	value = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;

	value |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);

	value &= ~DCCG_AUDIO_DTO1_USE_512FBR_DTO;

	WREG32(DCCG_AUDIO_DTO0_CNTL, value);



	/* Two dtos; generally use dto0 for HDMI */

	value = 0;



	if (crtc)

		value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);



	WREG32(DCCG_AUDIO_DTO_SOURCE, value);



	/* Express [24MHz / target pixel clock] as an exact rational

	 * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE

	 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator

	 */

	WREG32(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL(radeon_crtc->crtc_id));

	WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase);

	WREG32(DCCG_AUDIO_DTO0_MODULE, dto_modulo);

	WREG32(DCCG_AUDIO_DTO0_MODULE, clock);

}



void dce4_dp_audio_set_dto(struct radeon_device *rdev,

	struct radeon_crtc *crtc, unsigned int clock)

{

	u32 value;



	value = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;

	value |= DCCG_AUDIO_DTO1_USE_512FBR_DTO;

	WREG32(DCCG_AUDIO_DTO1_CNTL, value);



	/* Two dtos; generally use dto1 for DP */

	value = 0;

	value |= DCCG_AUDIO_DTO_SEL;



	if (crtc)

		value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);



	WREG32(DCCG_AUDIO_DTO_SOURCE, value);



	/* Express [24MHz / target pixel clock] as an exact rational

	 * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE

	 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator

	 */

	WREG32(DCCG_AUDIO_DTO1_PHASE, 24000);

	WREG32(DCCG_AUDIO_DTO1_MODULE, rdev->clock.max_pixel_clock * 10);

}



/*

 * update the info frames with the data from the current display mode
@@ -302,7 +322,7 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode 
	dig->afmt->pin = radeon_audio_get_pin(encoder);

	radeon_audio_enable(rdev, dig->afmt->pin, 0);



	evergreen_audio_set_dto(encoder, mode->clock);

	radeon_audio_set_dto(encoder, mode->clock);



	WREG32(HDMI_VBI_PACKET_CONTROL + offset,

	       HDMI_NULL_SEND); /* send null packets when required */

drivers/gpu/drm/radeon/evergreend.h

+1 −0
Original line number Diff line number Diff line
@@ -509,6 +509,7 @@ 
#define DCCG_AUDIO_DTO1_MODULE            0x05c4

#define DCCG_AUDIO_DTO1_LOAD              0x05c8

#define DCCG_AUDIO_DTO1_CNTL              0x05cc

#       define DCCG_AUDIO_DTO1_USE_512FBR_DTO (1 << 3)



/* DCE 4.0 AFMT */

#define HDMI_CONTROL                         0x7030

drivers/gpu/drm/radeon/r600_hdmi.c

+18 −62
Original line number Diff line number Diff line
@@ -380,75 +380,31 @@ void r600_hdmi_audio_workaround(struct drm_encoder *encoder) 
		 value, ~HDMI0_AUDIO_TEST_EN);

}



void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock)

void r600_hdmi_audio_set_dto(struct radeon_device *rdev,

    struct radeon_crtc *crtc, unsigned int clock)

{

	struct drm_device *dev = encoder->dev;

	struct radeon_device *rdev = dev->dev_private;

	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);

	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;

	u32 base_rate = 24000;

	u32 max_ratio = clock / base_rate;

	u32 dto_phase;

	u32 dto_modulo = clock;

	u32 wallclock_ratio;

	u32 dto_cntl;

	struct radeon_encoder *radeon_encoder;

	struct radeon_encoder_atom_dig *dig;



	if (!dig || !dig->afmt)

	if (!crtc)

		return;



	if (max_ratio >= 8) {

		dto_phase = 192 * 1000;

		wallclock_ratio = 3;

	} else if (max_ratio >= 4) {

		dto_phase = 96 * 1000;

		wallclock_ratio = 2;

	} else if (max_ratio >= 2) {

		dto_phase = 48 * 1000;

		wallclock_ratio = 1;

	} else {

		dto_phase = 24 * 1000;

		wallclock_ratio = 0;

	}

	radeon_encoder = to_radeon_encoder(crtc->encoder);

	dig = radeon_encoder->enc_priv;



	if (!dig)

		return;



	/* there are two DTOs selected by DCCG_AUDIO_DTO_SELECT.

	 * doesn't matter which one you use.  Just use the first one.

	 */

	/* XXX two dtos; generally use dto0 for hdmi */

	/* Express [24MHz / target pixel clock] as an exact rational

	 * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE

	 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator

	 */

	if (ASIC_IS_DCE32(rdev)) {

		if (dig->dig_encoder == 0) {

			dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;

			dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);

			WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl);

			WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase);

			WREG32(DCCG_AUDIO_DTO0_MODULE, dto_modulo);

			WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */

		} else {

			dto_cntl = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;

			dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);

			WREG32(DCCG_AUDIO_DTO1_CNTL, dto_cntl);

			WREG32(DCCG_AUDIO_DTO1_PHASE, dto_phase);

			WREG32(DCCG_AUDIO_DTO1_MODULE, dto_modulo);

			WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */

		}

	} else {

		/* according to the reg specs, this should DCE3.2 only, but in

		 * practice it seems to cover DCE2.0/3.0/3.1 as well.

		 */

	if (dig->dig_encoder == 0) {

			WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 100);

		WREG32(DCCG_AUDIO_DTO0_PHASE, 24000 * 100);

		WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100);

		WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */

	} else {

			WREG32(DCCG_AUDIO_DTO1_PHASE, base_rate * 100);

		WREG32(DCCG_AUDIO_DTO1_PHASE, 24000 * 100);

		WREG32(DCCG_AUDIO_DTO1_MODULE, clock * 100);

		WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */

	}

}

}



/*

 * update the info frames with the data from the current display mode
@@ -477,7 +433,7 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod 
	dig->afmt->pin = radeon_audio_get_pin(encoder);

	radeon_audio_enable(rdev, dig->afmt->pin, 0);



	r600_audio_set_dto(encoder, mode->clock);

	radeon_audio_set_dto(encoder, mode->clock);



	WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,

		 HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */

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