Commit a850c3f6 authored by Stephen Boyd's avatar Stephen Boyd Committed by David Brown
Browse files

msm: timer: Fix ONESHOT mode interrupts 



MSM timers don't support an interrupt enable/disable bit.
Therefore, when the timer is free running it's possible for the
count to wrap and the match value to match again even though a
set_next_event() call hasn't been made since the last match.

Workaround the lack of an interrupt enable bit by explicitly
stopping the timer in the interrupt handler when the clockevent
is in ONESHOT mode. This should prevent any possibility of the
timer wrapping and matching more than once per set_next_event().

Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: default avatarDavid Brown <davidb@codeaurora.org>
parent dd15ab81

arch/arm/mach-msm/timer.c

+20 −5
Original line number Diff line number Diff line
@@ -81,11 +81,20 @@ enum { 


static struct msm_clock msm_clocks[];



static struct msm_clock *clockevent_to_clock(struct clock_event_device *evt);



static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)

{

	struct clock_event_device *evt = *(struct clock_event_device **)dev_id;

	if (evt->event_handler == NULL)

		return IRQ_HANDLED;

	/* Stop the timer tick */

	if (evt->mode == CLOCK_EVT_MODE_ONESHOT) {

		struct msm_clock *clock = clockevent_to_clock(evt);

		u32 ctrl = readl_relaxed(clock->regbase + TIMER_ENABLE);

		ctrl &= ~TIMER_ENABLE_EN;

		writel_relaxed(ctrl, clock->regbase + TIMER_ENABLE);

	}

	evt->event_handler(evt);

	return IRQ_HANDLED;

}
@@ -118,10 +127,12 @@ static int msm_timer_set_next_event(unsigned long cycles, 
				    struct clock_event_device *evt)

{

	struct msm_clock *clock = clockevent_to_clock(evt);

	uint32_t now = readl(clock->local_counter);

	uint32_t alarm = now + (cycles << clock->shift);

	u32 match = cycles << clock->shift;

	u32 ctrl = readl_relaxed(clock->regbase + TIMER_ENABLE);



	writel(alarm, clock->regbase + TIMER_MATCH_VAL);

	writel_relaxed(0, clock->regbase + TIMER_CLEAR);

	writel_relaxed(match, clock->regbase + TIMER_MATCH_VAL);

	writel_relaxed(ctrl | TIMER_ENABLE_EN, clock->regbase + TIMER_ENABLE);

	return 0;

}
@@ -129,19 +140,23 @@ static void msm_timer_set_mode(enum clock_event_mode mode, 
			      struct clock_event_device *evt)

{

	struct msm_clock *clock = clockevent_to_clock(evt);

	u32 ctrl;



	ctrl = readl_relaxed(clock->regbase + TIMER_ENABLE);

	ctrl &= ~(TIMER_ENABLE_EN | TIMER_ENABLE_CLR_ON_MATCH_EN);



	switch (mode) {

	case CLOCK_EVT_MODE_RESUME:

	case CLOCK_EVT_MODE_PERIODIC:

		break;

	case CLOCK_EVT_MODE_ONESHOT:

		writel(TIMER_ENABLE_EN, clock->regbase + TIMER_ENABLE);

		/* Timer is enabled in set_next_event */

		break;

	case CLOCK_EVT_MODE_UNUSED:

	case CLOCK_EVT_MODE_SHUTDOWN:

		writel(0, clock->regbase + TIMER_ENABLE);

		break;

	}

	writel_relaxed(ctrl, clock->regbase + TIMER_ENABLE);

}



static struct msm_clock msm_clocks[] = {

CRA Git | Maintained and supported by SUSTech CRA and CCSE