drm/amdgpu: add parse clock gating state

static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);

static const struct cg_flag_name clocks[] = {

	{AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},

	{AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},

	{AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},

	{AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},

	{AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Light Sleep"},

	{AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},

	{AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},

	{AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},

	{AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},

	{AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},

	{AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},

	{AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},

	{AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},

	{AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},

	{AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},

	{AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},

	{AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},

	{AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},

	{0, NULL},

};

void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)

{

	if (adev->pp_enabled)

	return 0;

}

static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags)

{

	int i;

	for (i = 0; clocks[i].flag; i++)

		seq_printf(m, "\t%s: %s\n", clocks[i].name,

			   (flags & clocks[i].flag) ? "On" : "Off");

}

static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)

{

	struct drm_info_node *node = (struct drm_info_node *) m->private;

	amdgpu_get_clockgating_state(adev, &flags);

	seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags);

	amdgpu_parse_cg_state(m, flags);

	seq_printf(m, "\n");

	if (!adev->pm.dpm_enabled) {

		seq_printf(m, "dpm not enabled\n");

#ifndef __AMDGPU_PM_H__

#define __AMDGPU_PM_H__

struct cg_flag_name

{

	u32 flag;

	const char *name;

};

int amdgpu_pm_sysfs_init(struct amdgpu_device *adev);

void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev);

void amdgpu_pm_print_power_states(struct amdgpu_device *adev);