Commit a81abbb4 authored by Brian Norris's avatar Brian Norris Committed by Wim Van Sebroeck
Browse files

watchdog: dw: RMW the control register 



RK3399 has rst_pulse_length in CONTROL_REG[4:2], determining the length
of pulse to issue for system reset. We shouldn't clobber this value,
because that might make the system reset ineffective. On RK3399, we're
seeing that a value of 000b (meaning 2 cycles) yields an unreliable
(partial?) reset, and so we only fully reset after the watchdog fires a
second time. If we retain the system default (010b, or 8 clock cycles),
then the watchdog reset is much more reliable.

Read-modify-write retains the system value and improves reset
reliability.

It seems we were intentionally clobbering the response mode previously,
to ensure we performed a system reset (we don't support an interrupt
notification), so retain that explicitly.

Signed-off-by: default avatarBrian Norris <briannorris@chromium.org>
Reviewed-by: default avatarGuenter Roeck <linux@roeck-us.net>
Signed-off-by: default avatarGuenter Roeck <linux@roeck-us.net>
Signed-off-by: default avatarWim Van Sebroeck <wim@iguana.be>
parent 3c578cd4

drivers/watchdog/dw_wdt.c

+15 −8
Original line number Diff line number Diff line
@@ -34,6 +34,7 @@ 


#define WDOG_CONTROL_REG_OFFSET		    0x00

#define WDOG_CONTROL_REG_WDT_EN_MASK	    0x01

#define WDOG_CONTROL_REG_RESP_MODE_MASK	    0x02

#define WDOG_TIMEOUT_RANGE_REG_OFFSET	    0x04

#define WDOG_TIMEOUT_RANGE_TOPINIT_SHIFT    4

#define WDOG_CURRENT_COUNT_REG_OFFSET	    0x08
@@ -121,14 +122,23 @@ static int dw_wdt_set_timeout(struct watchdog_device *wdd, unsigned int top_s) 
	return 0;

}



static void dw_wdt_arm_system_reset(struct dw_wdt *dw_wdt)

{

	u32 val = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);



	/* Disable interrupt mode; always perform system reset. */

	val &= ~WDOG_CONTROL_REG_RESP_MODE_MASK;

	/* Enable watchdog. */

	val |= WDOG_CONTROL_REG_WDT_EN_MASK;

	writel(val, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);

}



static int dw_wdt_start(struct watchdog_device *wdd)

{

	struct dw_wdt *dw_wdt = to_dw_wdt(wdd);



	dw_wdt_set_timeout(wdd, wdd->timeout);



	writel(WDOG_CONTROL_REG_WDT_EN_MASK,

	       dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);

	dw_wdt_arm_system_reset(dw_wdt);



	return 0;

}
@@ -152,16 +162,13 @@ static int dw_wdt_restart(struct watchdog_device *wdd, 
			  unsigned long action, void *data)

{

	struct dw_wdt *dw_wdt = to_dw_wdt(wdd);

	u32 val;



	writel(0, dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);

	val = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);

	if (val & WDOG_CONTROL_REG_WDT_EN_MASK)

	if (dw_wdt_is_enabled(dw_wdt))

		writel(WDOG_COUNTER_RESTART_KICK_VALUE,

		       dw_wdt->regs + WDOG_COUNTER_RESTART_REG_OFFSET);

	else

		writel(WDOG_CONTROL_REG_WDT_EN_MASK,

		       dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);

		dw_wdt_arm_system_reset(dw_wdt);



	/* wait for reset to assert... */

	mdelay(500);

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