clk: meson-gxbb: Add video clocks (a8080f24) · Commits · 戴 / test

drivers/clk/meson/gxbb.c

+722 −0

Original line number	Diff line number	Diff line
		@@ -1558,6 +1558,616 @@ static struct clk_regmap gxbb_vapb = {
		},
		};

		/* Video Clocks */

		static struct clk_regmap gxbb_vid_pll_div = {
		.data = &(struct meson_vid_pll_div_data){
		.val = {
		.reg_off = HHI_VID_PLL_CLK_DIV,
		.shift = 0,
		.width = 15,
		},
		.sel = {
		.reg_off = HHI_VID_PLL_CLK_DIV,
		.shift = 16,
		.width = 2,
		},
		},
		.hw.init = &(struct clk_init_data) {
		.name = "vid_pll_div",
		.ops = &meson_vid_pll_div_ro_ops,
		.parent_names = (const char *[]){ "hdmi_pll" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT \| CLK_GET_RATE_NOCACHE,
		},
		};

		const char *gxbb_vid_pll_parent_names[] = { "vid_pll_div", "hdmi_pll" };

		static struct clk_regmap gxbb_vid_pll_sel = {
		.data = &(struct clk_regmap_mux_data){
		.offset = HHI_VID_PLL_CLK_DIV,
		.mask = 0x1,
		.shift = 18,
		},
		.hw.init = &(struct clk_init_data){
		.name = "vid_pll_sel",
		.ops = &clk_regmap_mux_ops,
		/*
		* bit 18 selects from 2 possible parents:
		* vid_pll_div or hdmi_pll
		*/
		.parent_names = gxbb_vid_pll_parent_names,
		.num_parents = ARRAY_SIZE(gxbb_vid_pll_parent_names),
		.flags = CLK_SET_RATE_NO_REPARENT \| CLK_GET_RATE_NOCACHE,
		},
		};

		static struct clk_regmap gxbb_vid_pll = {
		.data = &(struct clk_regmap_gate_data){
		.offset = HHI_VID_PLL_CLK_DIV,
		.bit_idx = 19,
		},
		.hw.init = &(struct clk_init_data) {
		.name = "vid_pll",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "vid_pll_sel" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
		},
		};

		const char *gxbb_vclk_parent_names[] = {
		"vid_pll", "fclk_div4", "fclk_div3", "fclk_div5", "vid_pll",
		"fclk_div7", "mpll1",
		};

		static struct clk_regmap gxbb_vclk_sel = {
		.data = &(struct clk_regmap_mux_data){
		.offset = HHI_VID_CLK_CNTL,
		.mask = 0x7,
		.shift = 16,
		},
		.hw.init = &(struct clk_init_data){
		.name = "vclk_sel",
		.ops = &clk_regmap_mux_ops,
		/*
		* bits 16:18 selects from 8 possible parents:
		* vid_pll, fclk_div4, fclk_div3, fclk_div5,
		* vid_pll, fclk_div7, mp1
		*/
		.parent_names = gxbb_vclk_parent_names,
		.num_parents = ARRAY_SIZE(gxbb_vclk_parent_names),
		.flags = CLK_SET_RATE_NO_REPARENT \| CLK_GET_RATE_NOCACHE,
		},
		};

		static struct clk_regmap gxbb_vclk2_sel = {
		.data = &(struct clk_regmap_mux_data){
		.offset = HHI_VIID_CLK_CNTL,
		.mask = 0x7,
		.shift = 16,
		},
		.hw.init = &(struct clk_init_data){
		.name = "vclk2_sel",
		.ops = &clk_regmap_mux_ops,
		/*
		* bits 16:18 selects from 8 possible parents:
		* vid_pll, fclk_div4, fclk_div3, fclk_div5,
		* vid_pll, fclk_div7, mp1
		*/
		.parent_names = gxbb_vclk_parent_names,
		.num_parents = ARRAY_SIZE(gxbb_vclk_parent_names),
		.flags = CLK_SET_RATE_NO_REPARENT \| CLK_GET_RATE_NOCACHE,
		},
		};

		static struct clk_regmap gxbb_vclk_input = {
		.data = &(struct clk_regmap_gate_data){
		.offset = HHI_VID_CLK_DIV,
		.bit_idx = 16,
		},
		.hw.init = &(struct clk_init_data) {
		.name = "vclk_input",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "vclk_sel" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
		},
		};

		static struct clk_regmap gxbb_vclk2_input = {
		.data = &(struct clk_regmap_gate_data){
		.offset = HHI_VIID_CLK_DIV,
		.bit_idx = 16,
		},
		.hw.init = &(struct clk_init_data) {
		.name = "vclk2_input",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "vclk2_sel" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
		},
		};

		static struct clk_regmap gxbb_vclk_div = {
		.data = &(struct clk_regmap_div_data){
		.offset = HHI_VID_CLK_DIV,
		.shift = 0,
		.width = 8,
		},
		.hw.init = &(struct clk_init_data){
		.name = "vclk_div",
		.ops = &clk_regmap_divider_ops,
		.parent_names = (const char *[]){ "vclk_input" },
		.num_parents = 1,
		.flags = CLK_GET_RATE_NOCACHE,
		},
		};

		static struct clk_regmap gxbb_vclk2_div = {
		.data = &(struct clk_regmap_div_data){
		.offset = HHI_VIID_CLK_DIV,
		.shift = 0,
		.width = 8,
		},
		.hw.init = &(struct clk_init_data){
		.name = "vclk2_div",
		.ops = &clk_regmap_divider_ops,
		.parent_names = (const char *[]){ "vclk2_input" },
		.num_parents = 1,
		.flags = CLK_GET_RATE_NOCACHE,
		},
		};

		static struct clk_regmap gxbb_vclk = {
		.data = &(struct clk_regmap_gate_data){
		.offset = HHI_VID_CLK_CNTL,
		.bit_idx = 19,
		},
		.hw.init = &(struct clk_init_data) {
		.name = "vclk",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "vclk_div" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
		},
		};

		static struct clk_regmap gxbb_vclk2 = {
		.data = &(struct clk_regmap_gate_data){
		.offset = HHI_VIID_CLK_CNTL,
		.bit_idx = 19,
		},
		.hw.init = &(struct clk_init_data) {
		.name = "vclk2",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "vclk2_div" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
		},
		};

		static struct clk_regmap gxbb_vclk_div1 = {
		.data = &(struct clk_regmap_gate_data){
		.offset = HHI_VID_CLK_CNTL,
		.bit_idx = 0,
		},
		.hw.init = &(struct clk_init_data) {
		.name = "vclk_div1",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "vclk" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
		},
		};

		static struct clk_regmap gxbb_vclk_div2_en = {
		.data = &(struct clk_regmap_gate_data){
		.offset = HHI_VID_CLK_CNTL,
		.bit_idx = 1,
		},
		.hw.init = &(struct clk_init_data) {
		.name = "vclk_div2_en",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "vclk" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
		},
		};

		static struct clk_regmap gxbb_vclk_div4_en = {
		.data = &(struct clk_regmap_gate_data){
		.offset = HHI_VID_CLK_CNTL,
		.bit_idx = 2,
		},
		.hw.init = &(struct clk_init_data) {
		.name = "vclk_div4_en",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "vclk" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
		},
		};

		static struct clk_regmap gxbb_vclk_div6_en = {
		.data = &(struct clk_regmap_gate_data){
		.offset = HHI_VID_CLK_CNTL,
		.bit_idx = 3,
		},
		.hw.init = &(struct clk_init_data) {
		.name = "vclk_div6_en",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "vclk" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
		},
		};

		static struct clk_regmap gxbb_vclk_div12_en = {
		.data = &(struct clk_regmap_gate_data){
		.offset = HHI_VID_CLK_CNTL,
		.bit_idx = 4,
		},
		.hw.init = &(struct clk_init_data) {
		.name = "vclk_div12_en",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "vclk" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
		},
		};

		static struct clk_regmap gxbb_vclk2_div1 = {
		.data = &(struct clk_regmap_gate_data){
		.offset = HHI_VIID_CLK_CNTL,
		.bit_idx = 0,
		},
		.hw.init = &(struct clk_init_data) {
		.name = "vclk2_div1",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "vclk2" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
		},
		};

		static struct clk_regmap gxbb_vclk2_div2_en = {
		.data = &(struct clk_regmap_gate_data){
		.offset = HHI_VIID_CLK_CNTL,
		.bit_idx = 1,
		},
		.hw.init = &(struct clk_init_data) {
		.name = "vclk2_div2_en",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "vclk2" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
		},
		};

		static struct clk_regmap gxbb_vclk2_div4_en = {
		.data = &(struct clk_regmap_gate_data){
		.offset = HHI_VIID_CLK_CNTL,
		.bit_idx = 2,
		},
		.hw.init = &(struct clk_init_data) {
		.name = "vclk2_div4_en",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "vclk2" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
		},
		};

		static struct clk_regmap gxbb_vclk2_div6_en = {
		.data = &(struct clk_regmap_gate_data){
		.offset = HHI_VIID_CLK_CNTL,
		.bit_idx = 3,
		},
		.hw.init = &(struct clk_init_data) {
		.name = "vclk2_div6_en",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "vclk2" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
		},
		};

		static struct clk_regmap gxbb_vclk2_div12_en = {
		.data = &(struct clk_regmap_gate_data){
		.offset = HHI_VIID_CLK_CNTL,
		.bit_idx = 4,
		},
		.hw.init = &(struct clk_init_data) {
		.name = "vclk2_div12_en",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "vclk2" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
		},
		};

		static struct clk_fixed_factor gxbb_vclk_div2 = {
		.mult = 1,
		.div = 2,
		.hw.init = &(struct clk_init_data){
		.name = "vclk_div2",
		.ops = &clk_fixed_factor_ops,
		.parent_names = (const char *[]){ "vclk_div2_en" },
		.num_parents = 1,
		},
		};

		static struct clk_fixed_factor gxbb_vclk_div4 = {
		.mult = 1,
		.div = 4,
		.hw.init = &(struct clk_init_data){
		.name = "vclk_div4",
		.ops = &clk_fixed_factor_ops,
		.parent_names = (const char *[]){ "vclk_div4_en" },
		.num_parents = 1,
		},
		};

		static struct clk_fixed_factor gxbb_vclk_div6 = {
		.mult = 1,
		.div = 6,
		.hw.init = &(struct clk_init_data){
		.name = "vclk_div6",
		.ops = &clk_fixed_factor_ops,
		.parent_names = (const char *[]){ "vclk_div6_en" },
		.num_parents = 1,
		},
		};

		static struct clk_fixed_factor gxbb_vclk_div12 = {
		.mult = 1,
		.div = 12,
		.hw.init = &(struct clk_init_data){
		.name = "vclk_div12",
		.ops = &clk_fixed_factor_ops,
		.parent_names = (const char *[]){ "vclk_div12_en" },
		.num_parents = 1,
		},
		};

		static struct clk_fixed_factor gxbb_vclk2_div2 = {
		.mult = 1,
		.div = 2,
		.hw.init = &(struct clk_init_data){
		.name = "vclk2_div2",
		.ops = &clk_fixed_factor_ops,
		.parent_names = (const char *[]){ "vclk2_div2_en" },
		.num_parents = 1,
		},
		};

		static struct clk_fixed_factor gxbb_vclk2_div4 = {
		.mult = 1,
		.div = 4,
		.hw.init = &(struct clk_init_data){
		.name = "vclk2_div4",
		.ops = &clk_fixed_factor_ops,
		.parent_names = (const char *[]){ "vclk2_div4_en" },
		.num_parents = 1,
		},
		};

		static struct clk_fixed_factor gxbb_vclk2_div6 = {
		.mult = 1,
		.div = 6,
		.hw.init = &(struct clk_init_data){
		.name = "vclk2_div6",
		.ops = &clk_fixed_factor_ops,
		.parent_names = (const char *[]){ "vclk2_div6_en" },
		.num_parents = 1,
		},
		};

		static struct clk_fixed_factor gxbb_vclk2_div12 = {
		.mult = 1,
		.div = 12,
		.hw.init = &(struct clk_init_data){
		.name = "vclk2_div12",
		.ops = &clk_fixed_factor_ops,
		.parent_names = (const char *[]){ "vclk2_div12_en" },
		.num_parents = 1,
		},
		};

		static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
		const char *gxbb_cts_parent_names[] = {
		"vclk_div1", "vclk_div2", "vclk_div4", "vclk_div6",
		"vclk_div12", "vclk2_div1", "vclk2_div2", "vclk2_div4",
		"vclk2_div6", "vclk2_div12"
		};

		static struct clk_regmap gxbb_cts_enci_sel = {
		.data = &(struct clk_regmap_mux_data){
		.offset = HHI_VID_CLK_DIV,
		.mask = 0xf,
		.shift = 28,
		.table = mux_table_cts_sel,
		},
		.hw.init = &(struct clk_init_data){
		.name = "cts_enci_sel",
		.ops = &clk_regmap_mux_ops,
		.parent_names = gxbb_cts_parent_names,
		.num_parents = ARRAY_SIZE(gxbb_cts_parent_names),
		.flags = CLK_SET_RATE_NO_REPARENT \| CLK_GET_RATE_NOCACHE,
		},
		};

		static struct clk_regmap gxbb_cts_encp_sel = {
		.data = &(struct clk_regmap_mux_data){
		.offset = HHI_VID_CLK_DIV,
		.mask = 0xf,
		.shift = 20,
		.table = mux_table_cts_sel,
		},
		.hw.init = &(struct clk_init_data){
		.name = "cts_encp_sel",
		.ops = &clk_regmap_mux_ops,
		.parent_names = gxbb_cts_parent_names,
		.num_parents = ARRAY_SIZE(gxbb_cts_parent_names),
		.flags = CLK_SET_RATE_NO_REPARENT \| CLK_GET_RATE_NOCACHE,
		},
		};

		static struct clk_regmap gxbb_cts_vdac_sel = {
		.data = &(struct clk_regmap_mux_data){
		.offset = HHI_VIID_CLK_DIV,
		.mask = 0xf,
		.shift = 28,
		.table = mux_table_cts_sel,
		},
		.hw.init = &(struct clk_init_data){
		.name = "cts_vdac_sel",
		.ops = &clk_regmap_mux_ops,
		.parent_names = gxbb_cts_parent_names,
		.num_parents = ARRAY_SIZE(gxbb_cts_parent_names),
		.flags = CLK_SET_RATE_NO_REPARENT \| CLK_GET_RATE_NOCACHE,
		},
		};

		/* TOFIX: add support for cts_tcon */
		static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
		const char *gxbb_cts_hdmi_tx_parent_names[] = {
		"vclk_div1", "vclk_div2", "vclk_div4", "vclk_div6",
		"vclk_div12", "vclk2_div1", "vclk2_div2", "vclk2_div4",
		"vclk2_div6", "vclk2_div12"
		};

		static struct clk_regmap gxbb_hdmi_tx_sel = {
		.data = &(struct clk_regmap_mux_data){
		.offset = HHI_HDMI_CLK_CNTL,
		.mask = 0xf,
		.shift = 16,
		.table = mux_table_hdmi_tx_sel,
		},
		.hw.init = &(struct clk_init_data){
		.name = "hdmi_tx_sel",
		.ops = &clk_regmap_mux_ops,
		/*
		* bits 31:28 selects from 12 possible parents:
		* vclk_div1, vclk_div2, vclk_div4, vclk_div6, vclk_div12
		* vclk2_div1, vclk2_div2, vclk2_div4, vclk2_div6, vclk2_div12,
		* cts_tcon
		*/
		.parent_names = gxbb_cts_hdmi_tx_parent_names,
		.num_parents = ARRAY_SIZE(gxbb_cts_hdmi_tx_parent_names),
		.flags = CLK_SET_RATE_NO_REPARENT \| CLK_GET_RATE_NOCACHE,
		},
		};

		static struct clk_regmap gxbb_cts_enci = {
		.data = &(struct clk_regmap_gate_data){
		.offset = HHI_VID_CLK_CNTL2,
		.bit_idx = 0,
		},
		.hw.init = &(struct clk_init_data) {
		.name = "cts_enci",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "cts_enci_sel" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
		},
		};

		static struct clk_regmap gxbb_cts_encp = {
		.data = &(struct clk_regmap_gate_data){
		.offset = HHI_VID_CLK_CNTL2,
		.bit_idx = 2,
		},
		.hw.init = &(struct clk_init_data) {
		.name = "cts_encp",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "cts_encp_sel" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
		},
		};

		static struct clk_regmap gxbb_cts_vdac = {
		.data = &(struct clk_regmap_gate_data){
		.offset = HHI_VID_CLK_CNTL2,
		.bit_idx = 4,
		},
		.hw.init = &(struct clk_init_data) {
		.name = "cts_vdac",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "cts_vdac_sel" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
		},
		};

		static struct clk_regmap gxbb_hdmi_tx = {
		.data = &(struct clk_regmap_gate_data){
		.offset = HHI_VID_CLK_CNTL2,
		.bit_idx = 5,
		},
		.hw.init = &(struct clk_init_data) {
		.name = "hdmi_tx",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "hdmi_tx_sel" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
		},
		};

		/* HDMI Clocks */

		static const char * const gxbb_hdmi_parent_names[] = {
		"xtal", "fclk_div4", "fclk_div3", "fclk_div5"
		};

		static struct clk_regmap gxbb_hdmi_sel = {
		.data = &(struct clk_regmap_mux_data){
		.offset = HHI_HDMI_CLK_CNTL,
		.mask = 0x3,
		.shift = 9,
		.flags = CLK_MUX_ROUND_CLOSEST,
		},
		.hw.init = &(struct clk_init_data){
		.name = "hdmi_sel",
		.ops = &clk_regmap_mux_ops,
		.parent_names = gxbb_hdmi_parent_names,
		.num_parents = ARRAY_SIZE(gxbb_hdmi_parent_names),
		.flags = CLK_SET_RATE_NO_REPARENT \| CLK_GET_RATE_NOCACHE,
		},
		};

		static struct clk_regmap gxbb_hdmi_div = {
		.data = &(struct clk_regmap_div_data){
		.offset = HHI_HDMI_CLK_CNTL,
		.shift = 0,
		.width = 7,
		},
		.hw.init = &(struct clk_init_data){
		.name = "hdmi_div",
		.ops = &clk_regmap_divider_ops,
		.parent_names = (const char *[]){ "hdmi_sel" },
		.num_parents = 1,
		.flags = CLK_GET_RATE_NOCACHE,
		},
		};

		static struct clk_regmap gxbb_hdmi = {
		.data = &(struct clk_regmap_gate_data){
		.offset = HHI_HDMI_CLK_CNTL,
		.bit_idx = 8,
		},
		.hw.init = &(struct clk_init_data) {
		.name = "hdmi",
		.ops = &clk_regmap_gate_ops,
		.parent_names = (const char *[]){ "hdmi_div" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
		},
		};

		/* VDEC clocks */

		static const char * const gxbb_vdec_parent_names[] = {
		@@ -1969,6 +2579,46 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
		[CLKID_HDMI_PLL_OD2] = &gxbb_hdmi_pll_od2.hw,
		[CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw,
		[CLKID_GP0_PLL_DCO] = &gxbb_gp0_pll_dco.hw,
		[CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw,
		[CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw,
		[CLKID_VID_PLL] = &gxbb_vid_pll.hw,
		[CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw,
		[CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw,
		[CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw,
		[CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw,
		[CLKID_VCLK_DIV] = &gxbb_vclk_div.hw,
		[CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw,
		[CLKID_VCLK] = &gxbb_vclk.hw,
		[CLKID_VCLK2] = &gxbb_vclk2.hw,
		[CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw,
		[CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw,
		[CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw,
		[CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw,
		[CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw,
		[CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw,
		[CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw,
		[CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw,
		[CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw,
		[CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw,
		[CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw,
		[CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw,
		[CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw,
		[CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw,
		[CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw,
		[CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw,
		[CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw,
		[CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw,
		[CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw,
		[CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw,
		[CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw,
		[CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw,
		[CLKID_CTS_ENCI] = &gxbb_cts_enci.hw,
		[CLKID_CTS_ENCP] = &gxbb_cts_encp.hw,
		[CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw,
		[CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw,
		[CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw,
		[CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw,
		[CLKID_HDMI] = &gxbb_hdmi.hw,
		[NR_CLKS] = NULL,
		},
		.num = NR_CLKS,
		@@ -2140,6 +2790,46 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = {
		[CLKID_HDMI_PLL_OD2] = &gxl_hdmi_pll_od2.hw,
		[CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw,
		[CLKID_GP0_PLL_DCO] = &gxl_gp0_pll_dco.hw,
		[CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw,
		[CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw,
		[CLKID_VID_PLL] = &gxbb_vid_pll.hw,
		[CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw,
		[CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw,
		[CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw,
		[CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw,
		[CLKID_VCLK_DIV] = &gxbb_vclk_div.hw,
		[CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw,
		[CLKID_VCLK] = &gxbb_vclk.hw,
		[CLKID_VCLK2] = &gxbb_vclk2.hw,
		[CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw,
		[CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw,
		[CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw,
		[CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw,
		[CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw,
		[CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw,
		[CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw,
		[CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw,
		[CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw,
		[CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw,
		[CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw,
		[CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw,
		[CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw,
		[CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw,
		[CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw,
		[CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw,
		[CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw,
		[CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw,
		[CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw,
		[CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw,
		[CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw,
		[CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw,
		[CLKID_CTS_ENCI] = &gxbb_cts_enci.hw,
		[CLKID_CTS_ENCP] = &gxbb_cts_encp.hw,
		[CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw,
		[CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw,
		[CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw,
		[CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw,
		[CLKID_HDMI] = &gxbb_hdmi.hw,
		[NR_CLKS] = NULL,
		},
		.num = NR_CLKS,
		@@ -2316,6 +3006,38 @@ static struct clk_regmap *const gx_clk_regmaps[] = {
		&gxbb_fixed_pll_dco,
		&gxbb_sys_pll_dco,
		&gxbb_gp0_pll,
		&gxbb_vid_pll,
		&gxbb_vid_pll_sel,
		&gxbb_vid_pll_div,
		&gxbb_vclk,
		&gxbb_vclk_sel,
		&gxbb_vclk_div,
		&gxbb_vclk_input,
		&gxbb_vclk_div1,
		&gxbb_vclk_div2_en,
		&gxbb_vclk_div4_en,
		&gxbb_vclk_div6_en,
		&gxbb_vclk_div12_en,
		&gxbb_vclk2,
		&gxbb_vclk2_sel,
		&gxbb_vclk2_div,
		&gxbb_vclk2_input,
		&gxbb_vclk2_div1,
		&gxbb_vclk2_div2_en,
		&gxbb_vclk2_div4_en,
		&gxbb_vclk2_div6_en,
		&gxbb_vclk2_div12_en,
		&gxbb_cts_enci,
		&gxbb_cts_enci_sel,
		&gxbb_cts_encp,
		&gxbb_cts_encp_sel,
		&gxbb_cts_vdac,
		&gxbb_cts_vdac_sel,
		&gxbb_hdmi_tx,
		&gxbb_hdmi_tx_sel,
		&gxbb_hdmi_sel,
		&gxbb_hdmi_div,
		&gxbb_hdmi,
		};

		struct clkc_data {

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