Commit a7fbc0d6 authored by Cyril Chemparathy's avatar Cyril Chemparathy Committed by Will Deacon
Browse files

ARM: LPAE: factor out T1SZ and TTBR1 computations 



This patch moves the TTBR1 offset calculation and the T1SZ calculation out
of the TTB setup assembly code.  This should not affect functionality in
any way, but improves code readability as well as readability of subsequent
patches in this series.

Signed-off-by: default avatarCyril Chemparathy <cyril@ti.com>
Signed-off-by: default avatarVitaly Andrianov <vitalya@ti.com>
Acked-by: default avatarNicolas Pitre <nico@linaro.org>
Tested-by: default avatarSantosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: default avatarSubash Patel <subash.rp@samsung.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent 1fc84ae8

arch/arm/include/asm/pgtable-3level-hwdef.h

+20 −0
Original line number Diff line number Diff line
@@ -79,4 +79,24 @@ 
#define PHYS_MASK_SHIFT		(40)

#define PHYS_MASK		((1ULL << PHYS_MASK_SHIFT) - 1)



/*

 * TTBR0/TTBR1 split (PAGE_OFFSET):

 *   0x40000000: T0SZ = 2, T1SZ = 0 (not used)

 *   0x80000000: T0SZ = 0, T1SZ = 1

 *   0xc0000000: T0SZ = 0, T1SZ = 2

 *

 * Only use this feature if PHYS_OFFSET <= PAGE_OFFSET, otherwise

 * booting secondary CPUs would end up using TTBR1 for the identity

 * mapping set up in TTBR0.

 */

#if defined CONFIG_VMSPLIT_2G

#define TTBR1_OFFSET	16			/* skip two L1 entries */

#elif defined CONFIG_VMSPLIT_3G

#define TTBR1_OFFSET	(4096 * (1 + 3))	/* only L2, skip pgd + 3*pmd */

#else

#define TTBR1_OFFSET	0

#endif



#define TTBR1_SIZE	(((PAGE_OFFSET >> 30) - 1) << 16)



#endif

arch/arm/mm/proc-v7-3level.S

+8 −21
Original line number Diff line number Diff line
@@ -114,7 +114,7 @@ ENDPROC(cpu_v7_set_pte_ext) 
	 */

	.macro	v7_ttb_setup, zero, ttbr0, ttbr1, tmp

	ldr	\tmp, =swapper_pg_dir		@ swapper_pg_dir virtual address

	cmp	\ttbr1, \tmp			@ PHYS_OFFSET > PAGE_OFFSET? (branch below)

	cmp	\ttbr1, \tmp			@ PHYS_OFFSET > PAGE_OFFSET?

	mrc	p15, 0, \tmp, c2, c0, 2		@ TTB control register

	orr	\tmp, \tmp, #TTB_EAE

	ALT_SMP(orr	\tmp, \tmp, #TTB_FLAGS_SMP)
@@ -122,26 +122,13 @@ ENDPROC(cpu_v7_set_pte_ext) 
	ALT_SMP(orr	\tmp, \tmp, #TTB_FLAGS_SMP << 16)

	ALT_UP(orr	\tmp, \tmp, #TTB_FLAGS_UP << 16)

	/*

	 * TTBR0/TTBR1 split (PAGE_OFFSET):

	 *   0x40000000: T0SZ = 2, T1SZ = 0 (not used)

	 *   0x80000000: T0SZ = 0, T1SZ = 1

	 *   0xc0000000: T0SZ = 0, T1SZ = 2

	 *

	 * Only use this feature if PHYS_OFFSET <= PAGE_OFFSET, otherwise

	 * booting secondary CPUs would end up using TTBR1 for the identity

	 * mapping set up in TTBR0.

	 * Only use split TTBRs if PHYS_OFFSET <= PAGE_OFFSET (cmp above),

	 * otherwise booting secondary CPUs would end up using TTBR1 for the

	 * identity mapping set up in TTBR0.

	 */

	bhi	9001f				@ PHYS_OFFSET > PAGE_OFFSET?

	orr	\tmp, \tmp, #(((PAGE_OFFSET >> 30) - 1) << 16) @ TTBCR.T1SZ

#if defined CONFIG_VMSPLIT_2G

	/* PAGE_OFFSET == 0x80000000, T1SZ == 1 */

	add	\ttbr1, \ttbr1, #1 << 4		@ skip two L1 entries

#elif defined CONFIG_VMSPLIT_3G

	/* PAGE_OFFSET == 0xc0000000, T1SZ == 2 */

	add	\ttbr1, \ttbr1, #4096 * (1 + 3)	@ only L2 used, skip pgd+3*pmd

#endif

	/* CONFIG_VMSPLIT_1G does not need TTBR1 adjustment */

9001:	mcr	p15, 0, \tmp, c2, c0, 2		@ TTB control register

	orrls	\tmp, \tmp, #TTBR1_SIZE				@ TTBCR.T1SZ

	mcr	p15, 0, \tmp, c2, c0, 2				@ TTBCR

	addls	\ttbr1, \ttbr1, #TTBR1_OFFSET

	mcrr	p15, 1, \ttbr1, \zero, c2			@ load TTBR1

	.endm

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