Commit a7f6e077 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'tegra-for-5.8-arm-core' of... 

Merge tag 'tegra-for-5.8-arm-core' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/soc

ARM: tegra: Core changes for v5.8-rc1

This contains core changes needed for the CPU frequency scaling and CPU
idle drivers on Tegra20 and Tegra30.

* tag 'tegra-for-5.8-arm-core' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  ARM: tegra: Create tegra20-cpufreq platform device on Tegra30
  ARM: tegra: Don't enable PLLX while resuming from LP1 on Tegra30
  ARM: tegra: Switch CPU to PLLP on resume from LP1 on Tegra30/114/124
  ARM: tegra: Correct PL310 Auxiliary Control Register initialization
  ARM: tegra: Do not fully reinitialize L2 on resume
  ARM: tegra: Initialize r0 register for firmware wake-up
  firmware: tf: Different way of L2 cache enabling after LP2 suspend
  firmware: tegra: Make BPMP a regular driver

Link: https://lore.kernel.org/r/20200515145311.1580134-10-thierry.reding@gmail.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents efb59c94 b9bf73ae

arch/arm/mach-tegra/pm.c

+4 −0
Original line number Diff line number Diff line
@@ -216,6 +216,8 @@ int tegra_pm_enter_lp2(void) 
	restore_cpu_complex();

	cpu_cluster_pm_exit();



	call_firmware_op(prepare_idle, TF_PM_MODE_NONE);



	return err;

}
@@ -391,6 +393,8 @@ static int tegra_suspend_enter(suspend_state_t state) 


	local_fiq_enable();



	call_firmware_op(prepare_idle, TF_PM_MODE_NONE);



	return 0;

}

arch/arm/mach-tegra/reset-handler.S

+6 −1
Original line number Diff line number Diff line
@@ -98,7 +98,12 @@ ENTRY(tegra_resume_trusted_foundations) 
	reteq	lr



 .arch_extension sec

	/* First call after suspend wakes firmware. No arguments required. */

	/*

	 * First call after suspend wakes firmware. No arguments required

	 * for some firmware versions. Downstream kernel of ASUS TF300T uses

	 * r0=3 for the wake-up notification.

	 */

	mov	r0, #3

	smc	#0



	b	cpu_resume

arch/arm/mach-tegra/sleep-tegra30.S

+9 −7
Original line number Diff line number Diff line
@@ -361,7 +361,6 @@ _no_pll_iddq_exit: 


	pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC

	pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC

	pll_enable r1, r0, CLK_RESET_PLLX_BASE, CLK_RESET_PLLX_MISC



_pll_m_c_x_done:

	pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC
@@ -371,12 +370,18 @@ _pll_m_c_x_done: 
	pll_locked r1, r0, CLK_RESET_PLLP_BASE

	pll_locked r1, r0, CLK_RESET_PLLA_BASE

	pll_locked r1, r0, CLK_RESET_PLLC_BASE

	pll_locked r1, r0, CLK_RESET_PLLX_BASE



	/*

	 * CPUFreq driver could select other PLL for CPU. PLLX will be

	 * enabled by the Tegra30 CLK driver on an as-needed basis, see

	 * tegra30_cpu_clock_resume().

	 */

	tegra_get_soc_id TEGRA_APB_MISC_BASE, r1

	cmp	r1, #TEGRA30

	beq	1f



	pll_locked r1, r0, CLK_RESET_PLLX_BASE



	ldr	r1, [r0, #CLK_RESET_PLLP_BASE]

	bic	r1, r1, #(1<<31)	@ disable PllP bypass

	str	r1, [r0, #CLK_RESET_PLLP_BASE]
@@ -398,11 +403,8 @@ _pll_m_c_x_done: 
	ldr	r4, [r5, #0x1C]		@ restore SCLK_BURST

	str	r4, [r0, #CLK_RESET_SCLK_BURST]



	cmp	r10, #TEGRA30

	movweq	r4, #:lower16:((1 << 28) | (0x8))	@ burst policy is PLLX

	movteq	r4, #:upper16:((1 << 28) | (0x8))

	movwne	r4, #:lower16:((1 << 28) | (0xe))

	movtne	r4, #:upper16:((1 << 28) | (0xe))

	movw	r4, #:lower16:((1 << 28) | (0x4))	@ burst policy is PLLP

	movt	r4, #:upper16:((1 << 28) | (0x4))

	str	r4, [r0, #CLK_RESET_CCLK_BURST]



	/* Restore pad power state to normal */

arch/arm/mach-tegra/tegra.c

+6 −2
Original line number Diff line number Diff line
@@ -96,6 +96,10 @@ static void __init tegra_dt_init_late(void) 


	if (IS_ENABLED(CONFIG_ARM_TEGRA_CPUIDLE) && !psci_smp_available())

		platform_device_register_simple("tegra-cpuidle", -1, NULL, 0);



	if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) &&

	    of_machine_is_compatible("nvidia,tegra30"))

		platform_device_register_simple("tegra20-cpufreq", -1, NULL, 0);

}



static const char * const tegra_dt_board_compat[] = {
@@ -107,8 +111,8 @@ static const char * const tegra_dt_board_compat[] = { 
};



DT_MACHINE_START(TEGRA_DT, "NVIDIA Tegra SoC (Flattened Device Tree)")

	.l2c_aux_val	= 0x3c400001,

	.l2c_aux_mask	= 0xc20fc3fe,

	.l2c_aux_val	= 0x3c400000,

	.l2c_aux_mask	= 0xc20fc3ff,

	.smp		= smp_ops(tegra_smp_ops),

	.map_io		= tegra_map_common_io,

	.init_early	= tegra_init_early,

drivers/firmware/tegra/bpmp.c

+3 −6
Original line number Diff line number Diff line
@@ -6,6 +6,7 @@ 
#include <linux/clk/tegra.h>

#include <linux/genalloc.h>

#include <linux/mailbox_client.h>

#include <linux/module.h>

#include <linux/of.h>

#include <linux/of_address.h>

#include <linux/of_device.h>
@@ -869,12 +870,8 @@ static struct platform_driver tegra_bpmp_driver = { 
		.name = "tegra-bpmp",

		.of_match_table = tegra_bpmp_match,

		.pm = &tegra_bpmp_pm_ops,

		.suppress_bind_attrs = true,

	},

	.probe = tegra_bpmp_probe,

};



static int __init tegra_bpmp_init(void)

{

	return platform_driver_register(&tegra_bpmp_driver);

}

core_initcall(tegra_bpmp_init);
 
builtin_platform_driver(tegra_bpmp_driver);

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