Unverified Commit a7db690c authored by Jernej Skrabec's avatar Jernej Skrabec Committed by Maxime Ripard
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drm/sun4i: Improve VI scaling for DE2/DE3 



VI planes support coarse scaling which helps to overcome VI scaler
limitations. While exact working of coarse scaling isn't known, it seems
that it just skips programmed amount of rows and columns. This is
especially useful for downscaling very big planes (4K down to 1080p).

Horizontal coarse scaling is currently used to fit one line to VI scaler
buffer.

Vertical coarse scaling is used to assure that VI scaler is actually
capable of processing framebuffer in one frame time.

Signed-off-by: default avatarJernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190228200329.11128-4-jernej.skrabec@siol.net
parent 2586de70

drivers/gpu/drm/sun4i/sun8i_vi_layer.c

+51 −3
Original line number Diff line number Diff line
@@ -80,6 +80,8 @@ static int sun8i_vi_layer_update_coord(struct sun8i_mixer *mixer, int channel, 
	u32 bld_base, ch_base;

	u32 outsize, insize;

	u32 hphase, vphase;

	u32 hn = 0, hm = 0;

	u32 vn = 0, vm = 0;

	bool subsampled;



	DRM_DEBUG_DRIVER("Updating VI channel %d overlay %d\n",
@@ -137,12 +139,41 @@ static int sun8i_vi_layer_update_coord(struct sun8i_mixer *mixer, int channel, 
	subsampled = format->hsub > 1 || format->vsub > 1;



	if (insize != outsize || subsampled || hphase || vphase) {

		u32 hscale, vscale;

		unsigned int scanline, required;

		struct drm_display_mode *mode;

		u32 hscale, vscale, fps;

		u64 ability;



		DRM_DEBUG_DRIVER("HW scaling is enabled\n");



		hscale = state->src_w / state->crtc_w;

		vscale = state->src_h / state->crtc_h;

		mode = &plane->state->crtc->state->mode;

		fps = (mode->clock * 1000) / (mode->vtotal * mode->htotal);

		ability = clk_get_rate(mixer->mod_clk);

		/* BSP algorithm assumes 80% efficiency of VI scaler unit */

		ability *= 80;

		do_div(ability, mode->vdisplay * fps * max(src_w, dst_w));



		required = src_h * 100 / dst_h;



		if (ability < required) {

			DRM_DEBUG_DRIVER("Using vertical coarse scaling\n");

			vm = src_h;

			vn = (u32)ability * dst_h / 100;

			src_h = vn;

		}



		/* it seems that every RGB scaler has buffer for 2048 pixels */

		scanline = subsampled ? mixer->cfg->scanline_yuv : 2048;



		if (src_w > scanline) {

			DRM_DEBUG_DRIVER("Using horizontal coarse scaling\n");

			hm = src_w;

			hn = scanline;

			src_w = hn;

		}



		hscale = (src_w << 16) / dst_w;

		vscale = (src_h << 16) / dst_h;



		sun8i_vi_scaler_setup(mixer, channel, src_w, src_h, dst_w,

				      dst_h, hscale, vscale, hphase, vphase,
@@ -153,6 +184,23 @@ static int sun8i_vi_layer_update_coord(struct sun8i_mixer *mixer, int channel, 
		sun8i_vi_scaler_enable(mixer, channel, false);

	}



	regmap_write(mixer->engine.regs,

		     SUN8I_MIXER_CHAN_VI_HDS_Y(ch_base),

		     SUN8I_MIXER_CHAN_VI_DS_N(hn) |

		     SUN8I_MIXER_CHAN_VI_DS_M(hm));

	regmap_write(mixer->engine.regs,

		     SUN8I_MIXER_CHAN_VI_HDS_UV(ch_base),

		     SUN8I_MIXER_CHAN_VI_DS_N(hn) |

		     SUN8I_MIXER_CHAN_VI_DS_M(hm));

	regmap_write(mixer->engine.regs,

		     SUN8I_MIXER_CHAN_VI_VDS_Y(ch_base),

		     SUN8I_MIXER_CHAN_VI_DS_N(vn) |

		     SUN8I_MIXER_CHAN_VI_DS_M(vm));

	regmap_write(mixer->engine.regs,

		     SUN8I_MIXER_CHAN_VI_VDS_UV(ch_base),

		     SUN8I_MIXER_CHAN_VI_DS_N(vn) |

		     SUN8I_MIXER_CHAN_VI_DS_M(vm));



	/* Set base coordinates */

	DRM_DEBUG_DRIVER("Layer destination coordinates X: %d Y: %d\n",

			 state->dst.x1, state->dst.y1);

drivers/gpu/drm/sun4i/sun8i_vi_layer.h

+11 −0
Original line number Diff line number Diff line
@@ -24,6 +24,14 @@ 
		((base) + 0x30 * (layer) + 0x18 + 4 * (plane))

#define SUN8I_MIXER_CHAN_VI_OVL_SIZE(base) \

		((base) + 0xe8)

#define SUN8I_MIXER_CHAN_VI_HDS_Y(base) \

		((base) + 0xf0)

#define SUN8I_MIXER_CHAN_VI_HDS_UV(base) \

		((base) + 0xf4)

#define SUN8I_MIXER_CHAN_VI_VDS_Y(base) \

		((base) + 0xf8)

#define SUN8I_MIXER_CHAN_VI_VDS_UV(base) \

		((base) + 0xfc)



#define SUN8I_MIXER_CHAN_VI_LAYER_ATTR_EN		BIT(0)

/* RGB mode should be set for RGB formats and cleared for YCbCr */
@@ -33,6 +41,9 @@ 
#define SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA_MASK	GENMASK(31, 24)

#define SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA(x)	((x) << 24)



#define SUN8I_MIXER_CHAN_VI_DS_N(x)			((x) << 16)

#define SUN8I_MIXER_CHAN_VI_DS_M(x)			((x) << 0)



struct sun8i_mixer;



struct sun8i_vi_layer {

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