Commit a7cb4671 authored by Tony Lindgren's avatar Tony Lindgren
Browse files

ARM: OMAP2+: Drop unused legacy data for prcm_reg_id and module_bit 



We are now using clock drivers in driver/clk/ti for enabling and disabling
modules and these are all unused.

Let's also remove the related unused defines in cm-regbits-24xx.h and
cm-regbits-34xx.h.

Reported-by: default avatarH. Nikolaus Schaller <hns@goldelico.com>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent fdf36329

arch/arm/mach-omap2/cm-regbits-24xx.h

+0 −81
Original line number Diff line number Diff line
@@ -14,38 +14,8 @@ 
 * published by the Free Software Foundation.

 */



#define OMAP24XX_EN_CAM_SHIFT				31

#define OMAP24XX_EN_WDT4_SHIFT				29

#define OMAP2420_EN_WDT3_SHIFT				28

#define OMAP24XX_EN_MSPRO_SHIFT				27

#define OMAP24XX_EN_FAC_SHIFT				25

#define OMAP2420_EN_EAC_SHIFT				24

#define OMAP24XX_EN_HDQ_SHIFT				23

#define OMAP2420_EN_I2C2_SHIFT				20

#define OMAP2420_EN_I2C1_SHIFT				19

#define OMAP2430_EN_MCBSP5_SHIFT			5

#define OMAP2430_EN_MCBSP4_SHIFT			4

#define OMAP2430_EN_MCBSP3_SHIFT			3

#define OMAP24XX_EN_SSI_SHIFT				1

#define OMAP24XX_EN_MPU_WDT_SHIFT			3

#define OMAP24XX_CLKSEL_MPU_SHIFT			0

#define OMAP24XX_CLKSEL_MPU_WIDTH			5

#define OMAP24XX_AUTOSTATE_MPU_MASK			(1 << 0)

#define OMAP24XX_EN_TV_SHIFT				2

#define OMAP24XX_EN_DSS2_SHIFT				1

#define OMAP24XX_EN_DSS1_SHIFT				0

#define OMAP24XX_EN_DSS1_MASK				(1 << 0)

#define OMAP2430_EN_I2CHS2_SHIFT			20

#define OMAP2430_EN_I2CHS1_SHIFT			19

#define OMAP2430_EN_MMCHSDB2_SHIFT			17

#define OMAP2430_EN_MMCHSDB1_SHIFT			16

#define OMAP24XX_EN_MAILBOXES_SHIFT			30

#define OMAP2430_EN_SDRC_SHIFT				2

#define OMAP24XX_EN_PKA_SHIFT				4

#define OMAP24XX_EN_AES_SHIFT				3

#define OMAP24XX_EN_RNG_SHIFT				2

#define OMAP24XX_EN_SHA_SHIFT				1

#define OMAP24XX_EN_DES_SHIFT				0

#define OMAP24XX_ST_MAILBOXES_SHIFT			30

#define OMAP24XX_ST_HDQ_SHIFT				23

#define OMAP2420_ST_I2C2_SHIFT				20
@@ -54,81 +24,30 @@ 
#define OMAP2430_ST_I2CHS2_SHIFT			20

#define OMAP24XX_ST_MCBSP2_SHIFT			16

#define OMAP24XX_ST_MCBSP1_SHIFT			15

#define OMAP24XX_ST_DSS_SHIFT				0

#define OMAP2430_ST_MCBSP5_SHIFT			5

#define OMAP2430_ST_MCBSP4_SHIFT			4

#define OMAP2430_ST_MCBSP3_SHIFT			3

#define OMAP24XX_ST_AES_SHIFT				3

#define OMAP24XX_ST_RNG_SHIFT				2

#define OMAP24XX_ST_SHA_SHIFT				1

#define OMAP24XX_AUTO_SDRC_SHIFT			2

#define OMAP24XX_AUTO_GPMC_SHIFT			1

#define OMAP24XX_AUTO_SDMA_SHIFT			0

#define OMAP24XX_CLKSEL_USB_MASK			(0x7 << 25)

#define OMAP24XX_CLKSEL_SSI_MASK			(0x1f << 20)

#define OMAP2420_CLKSEL_VLYNQ_MASK			(0x1f << 15)

#define OMAP24XX_CLKSEL_DSS2_MASK			(0x1 << 13)

#define OMAP24XX_CLKSEL_DSS1_MASK			(0x1f << 8)

#define OMAP24XX_CLKSEL_L4_SHIFT			5

#define OMAP24XX_CLKSEL_L4_WIDTH			2

#define OMAP24XX_CLKSEL_L3_SHIFT			0

#define OMAP24XX_CLKSEL_L3_WIDTH			5

#define OMAP24XX_CLKSEL_GPT12_MASK			(0x3 << 22)

#define OMAP24XX_CLKSEL_GPT11_MASK			(0x3 << 20)

#define OMAP24XX_CLKSEL_GPT10_MASK			(0x3 << 18)

#define OMAP24XX_CLKSEL_GPT9_MASK			(0x3 << 16)

#define OMAP24XX_CLKSEL_GPT8_MASK			(0x3 << 14)

#define OMAP24XX_CLKSEL_GPT7_MASK			(0x3 << 12)

#define OMAP24XX_CLKSEL_GPT6_MASK			(0x3 << 10)

#define OMAP24XX_CLKSEL_GPT5_MASK			(0x3 << 8)

#define OMAP24XX_CLKSEL_GPT4_MASK			(0x3 << 6)

#define OMAP24XX_CLKSEL_GPT3_MASK			(0x3 << 4)

#define OMAP24XX_CLKSEL_GPT2_MASK			(0x3 << 2)

#define OMAP24XX_AUTOSTATE_DSS_MASK			(1 << 2)

#define OMAP24XX_AUTOSTATE_L4_MASK			(1 << 1)

#define OMAP24XX_AUTOSTATE_L3_MASK			(1 << 0)

#define OMAP24XX_EN_3D_SHIFT				2

#define OMAP24XX_EN_2D_SHIFT				1

#define OMAP24XX_AUTOSTATE_GFX_MASK			(1 << 0)

#define OMAP2430_EN_ICR_SHIFT				6

#define OMAP24XX_EN_OMAPCTRL_SHIFT			5

#define OMAP24XX_EN_WDT1_SHIFT				4

#define OMAP24XX_EN_32KSYNC_SHIFT			1

#define OMAP24XX_ST_MPU_WDT_SHIFT			3

#define OMAP24XX_ST_32KSYNC_SHIFT			1

#define OMAP24XX_CLKSEL_GPT1_MASK			(0x3 << 0)

#define OMAP24XX_EN_54M_PLL_SHIFT			6

#define OMAP24XX_EN_96M_PLL_SHIFT			2

#define OMAP24XX_EN_DPLL_MASK				(0x3 << 0)

#define OMAP24XX_ST_54M_APLL_SHIFT			9

#define OMAP24XX_ST_96M_APLL_SHIFT			8

#define OMAP24XX_AUTO_54M_MASK				(0x3 << 6)

#define OMAP24XX_AUTO_96M_MASK				(0x3 << 2)

#define OMAP24XX_AUTO_DPLL_SHIFT			0

#define OMAP24XX_AUTO_DPLL_MASK				(0x3 << 0)

#define OMAP24XX_APLLS_CLKIN_SHIFT			23

#define OMAP24XX_APLLS_CLKIN_WIDTH			3

#define OMAP24XX_APLLS_CLKIN_MASK			(0x7 << 23)

#define OMAP24XX_DPLL_MULT_MASK				(0x3ff << 12)

#define OMAP24XX_DPLL_DIV_MASK				(0xf << 8)

#define OMAP24XX_54M_SOURCE_SHIFT			5

#define OMAP24XX_54M_SOURCE_WIDTH			1

#define OMAP2430_96M_SOURCE_SHIFT			4

#define OMAP2430_96M_SOURCE_WIDTH			1

#define OMAP24XX_48M_SOURCE_MASK			(1 << 3)

#define OMAP24XX_CORE_CLK_SRC_MASK			(0x3 << 0)

#define OMAP2420_EN_IVA_COP_SHIFT			10

#define OMAP2420_EN_IVA_MPU_SHIFT			8

#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT		0

#define OMAP2420_EN_DSP_IPI_SHIFT			1

#define OMAP2420_CLKSEL_IVA_MASK			(0x1f << 8)

#define OMAP24XX_CLKSEL_DSP_IF_MASK			(0x3 << 5)

#define OMAP24XX_CLKSEL_DSP_MASK			(0x1f << 0)

#define OMAP2420_AUTOSTATE_IVA_MASK			(1 << 8)

#define OMAP24XX_AUTOSTATE_DSP_MASK			(1 << 0)

#define OMAP2430_EN_OSC_SHIFT				1

#define OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT		0

#define OMAP2430_CLKSEL_MDM_MASK			(0xf << 0)

#define OMAP2430_AUTOSTATE_MDM_MASK			(1 << 0)

#define OMAP24XX_CLKSTCTRL_DISABLE_AUTO		0x0

#define OMAP24XX_CLKSTCTRL_ENABLE_AUTO		0x1

arch/arm/mach-omap2/cm-regbits-34xx.h

+0 −162
Original line number Diff line number Diff line
@@ -14,68 +14,11 @@ 
 * published by the Free Software Foundation.

 */



#define OMAP3430ES2_EN_MMC3_SHIFT			30

#define OMAP3430_EN_MSPRO_SHIFT				23

#define OMAP3430_EN_HDQ_SHIFT				22

#define OMAP3430ES1_EN_FSHOSTUSB_SHIFT			5

#define OMAP3430ES1_EN_D2D_SHIFT			3

#define OMAP3430_EN_SSI_SHIFT				0

#define OMAP3430ES2_EN_USBTLL_SHIFT			2

#define OMAP3430_EN_WDT2_SHIFT				5

#define OMAP3430_EN_CAM_SHIFT				0

#define OMAP3430_EN_WDT3_SHIFT				12

#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK		(1 << 0)

#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT		0

#define OMAP3430_IVA2_DPLL_FREQSEL_SHIFT		4

#define OMAP3430_IVA2_DPLL_FREQSEL_MASK			(0xf << 4)

#define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT		3

#define OMAP3430_EN_IVA2_DPLL_SHIFT			0

#define OMAP3430_EN_IVA2_DPLL_MASK			(0x7 << 0)

#define OMAP3430_ST_IVA2_SHIFT				0

#define OMAP3430_ST_IVA2_CLK_MASK			(1 << 0)

#define OMAP3430_AUTO_IVA2_DPLL_SHIFT			0

#define OMAP3430_AUTO_IVA2_DPLL_MASK			(0x7 << 0)

#define OMAP3430_IVA2_CLK_SRC_SHIFT			19

#define OMAP3430_IVA2_CLK_SRC_WIDTH			3

#define OMAP3430_IVA2_DPLL_MULT_MASK			(0x7ff << 8)

#define OMAP3430_IVA2_DPLL_DIV_MASK			(0x7f << 0)

#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT		0

#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_WIDTH		5

#define OMAP3430_CLKTRCTRL_IVA2_MASK			(0x3 << 0)

#define OMAP3430_CLKACTIVITY_IVA2_MASK			(1 << 0)

#define OMAP3430_MPU_DPLL_FREQSEL_MASK			(0xf << 4)

#define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT		3

#define OMAP3430_EN_MPU_DPLL_MASK			(0x7 << 0)

#define OMAP3430_ST_MPU_CLK_SHIFT			0

#define OMAP3430_ST_MPU_CLK_MASK			(1 << 0)

#define OMAP3430_ST_MPU_CLK_WIDTH			1

#define OMAP3430_AUTO_MPU_DPLL_MASK			(0x7 << 0)

#define OMAP3430_MPU_CLK_SRC_SHIFT			19

#define OMAP3430_MPU_CLK_SRC_WIDTH			3

#define OMAP3430_MPU_DPLL_MULT_MASK			(0x7ff << 8)

#define OMAP3430_MPU_DPLL_DIV_MASK			(0x7f << 0)

#define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT		0

#define OMAP3430_MPU_DPLL_CLKOUT_DIV_WIDTH		5

#define OMAP3430_CLKTRCTRL_MPU_MASK			(0x3 << 0)

#define OMAP3430_EN_MODEM_SHIFT				31

#define OMAP3430_EN_ICR_SHIFT				29

#define OMAP3430_EN_AES2_SHIFT				28

#define OMAP3430_EN_SHA12_SHIFT				27

#define OMAP3430_EN_DES2_SHIFT				26

#define OMAP3430ES1_EN_FAC_SHIFT			8

#define OMAP3430_EN_MAILBOXES_SHIFT			7

#define OMAP3430_EN_OMAPCTRL_SHIFT			6

#define OMAP3430_EN_SAD2D_SHIFT				3

#define OMAP3430_EN_SDRC_SHIFT				1

#define AM35XX_EN_IPSS_SHIFT				4

#define OMAP3430_EN_PKA_SHIFT				4

#define OMAP3430_EN_AES1_SHIFT				3

#define OMAP3430_EN_RNG_SHIFT				2

#define OMAP3430_EN_SHA11_SHIFT				1

#define OMAP3430_EN_DES1_SHIFT				0

#define OMAP3430_EN_MAD2D_SHIFT				3

#define OMAP3430ES2_EN_TS_SHIFT				1

#define OMAP3430ES2_EN_CPEFUSE_SHIFT			0

#define OMAP3430_ST_AES2_SHIFT				28

#define OMAP3430_ST_SHA12_SHIFT				27

#define AM35XX_ST_UART4_SHIFT				23
@@ -84,131 +27,26 @@ 
#define OMAP3430_ST_MAILBOXES_SHIFT			7

#define OMAP3430_ST_SAD2D_SHIFT				3

#define OMAP3430_ST_SDMA_SHIFT				2

#define AM35XX_ST_IPSS_SHIFT				5

#define OMAP3430ES2_ST_USBTLL_SHIFT			2

#define OMAP3430_CLKSEL_SSI_MASK			(0xf << 8)

#define OMAP3430_CLKSEL_GPT11_MASK			(1 << 7)

#define OMAP3430_CLKSEL_GPT10_MASK			(1 << 6)

#define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK		(0x3 << 4)

#define OMAP3430_CLKSEL_L4_SHIFT			2

#define OMAP3430_CLKSEL_L4_WIDTH			2

#define OMAP3430_CLKSEL_L3_SHIFT			0

#define OMAP3430_CLKSEL_L3_WIDTH			2

#define OMAP3630_CLKSEL_96M_MASK			(0x3 << 12)

#define OMAP3430ES1_CLKTRCTRL_D2D_MASK			(0x3 << 4)

#define OMAP3430_CLKTRCTRL_L4_MASK			(0x3 << 2)

#define OMAP3430_CLKTRCTRL_L3_MASK			(0x3 << 0)

#define OMAP3430ES1_EN_3D_SHIFT				2

#define OMAP3430ES1_EN_2D_SHIFT				1

#define OMAP3430ES1_CLKTRCTRL_GFX_MASK			(0x3 << 0)

#define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT		1

#define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT		0

#define OMAP3430ES2_CLKSEL_SGX_MASK			(0x7 << 0)

#define OMAP3430ES2_CLKTRCTRL_SGX_MASK			(0x3 << 0)

#define OMAP3430ES2_EN_USIMOCP_SHIFT			9

#define OMAP3430_EN_WDT1_SHIFT				4

#define OMAP3430_EN_32KSYNC_SHIFT			2

#define OMAP3430_ST_WDT2_SHIFT				5

#define OMAP3430_ST_32KSYNC_SHIFT			2

#define OMAP3430ES2_CLKSEL_USIMOCP_MASK			(0xf << 3)

#define OMAP3430_CLKSEL_RM_SHIFT			1

#define OMAP3430_CLKSEL_RM_WIDTH			2

#define OMAP3430_CLKSEL_GPT1_MASK			(1 << 0)

#define OMAP3430_PWRDN_EMU_PERIPH_SHIFT			31

#define OMAP3430_PWRDN_CAM_SHIFT			30

#define OMAP3430_PWRDN_DSS1_SHIFT			29

#define OMAP3430_PWRDN_TV_SHIFT				28

#define OMAP3430_PWRDN_96M_SHIFT			27

#define OMAP3430_PERIPH_DPLL_FREQSEL_MASK		(0xf << 20)

#define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT	19

#define OMAP3430_EN_PERIPH_DPLL_MASK			(0x7 << 16)

#define OMAP3430_PWRDN_EMU_CORE_SHIFT			12

#define OMAP3430_CORE_DPLL_FREQSEL_MASK			(0xf << 4)

#define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT		3

#define OMAP3430_EN_CORE_DPLL_MASK			(0x7 << 0)

#define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK		(0xf << 4)

#define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT	3

#define OMAP3430ES2_EN_PERIPH2_DPLL_MASK		(0x7 << 0)

#define OMAP3430_ST_PERIPH_CLK_MASK			(1 << 1)

#define OMAP3430_ST_CORE_CLK_MASK			(1 << 0)

#define OMAP3430ES2_ST_PERIPH2_CLK_MASK			(1 << 0)

#define OMAP3430_AUTO_PERIPH_DPLL_MASK			(0x7 << 3)

#define OMAP3430_AUTO_CORE_DPLL_MASK			(0x7 << 0)

#define OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK		(0x7 << 0)

#define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT		27

#define OMAP3430_CORE_DPLL_CLKOUT_DIV_WIDTH		5

#define OMAP3430_CORE_DPLL_MULT_MASK			(0x7ff << 16)

#define OMAP3430_CORE_DPLL_DIV_MASK			(0x7f << 8)

#define OMAP3430_SOURCE_96M_SHIFT			6

#define OMAP3430_SOURCE_96M_WIDTH			1

#define OMAP3430_SOURCE_54M_SHIFT			5

#define OMAP3430_SOURCE_54M_WIDTH			1

#define OMAP3430_SOURCE_48M_MASK			(1 << 3)

#define OMAP3430_PERIPH_DPLL_MULT_MASK			(0x7ff << 8)

#define OMAP3630_PERIPH_DPLL_MULT_MASK			(0xfff << 8)

#define OMAP3430_PERIPH_DPLL_DIV_MASK			(0x7f << 0)

#define OMAP3630_PERIPH_DPLL_DCO_SEL_MASK		(0x7 << 21)

#define OMAP3630_PERIPH_DPLL_SD_DIV_MASK		(0xff << 24)

#define OMAP3430_DIV_96M_SHIFT				0

#define OMAP3630_DIV_96M_WIDTH				6

#define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK		(0x7ff << 8)

#define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK		(0x7f << 0)

#define OMAP3430ES2_DIV_120M_SHIFT			0

#define OMAP3430ES2_DIV_120M_WIDTH			5

#define OMAP3430_CLKOUT2_EN_SHIFT			7

#define OMAP3430_CLKOUT2_DIV_SHIFT			3

#define OMAP3430_CLKOUT2_DIV_WIDTH			3

#define OMAP3430_CLKOUT2SOURCE_MASK			(0x3 << 0)

#define OMAP3430_EN_TV_SHIFT				2

#define OMAP3430_EN_DSS2_SHIFT				1

#define OMAP3430_EN_DSS1_SHIFT				0

#define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT		0

#define OMAP3430ES2_ST_DSS_IDLE_SHIFT			1

#define OMAP3430ES2_ST_DSS_STDBY_SHIFT			0

#define OMAP3430ES1_ST_DSS_SHIFT			0

#define OMAP3430_CLKSEL_TV_SHIFT			8

#define OMAP3630_CLKSEL_TV_WIDTH			6

#define OMAP3430_CLKSEL_DSS1_SHIFT			0

#define OMAP3630_CLKSEL_DSS1_WIDTH			6

#define OMAP3430_CLKTRCTRL_DSS_MASK			(0x3 << 0)

#define OMAP3430_EN_CSI2_SHIFT				1

#define OMAP3430_CLKSEL_CAM_SHIFT			0

#define OMAP3630_CLKSEL_CAM_WIDTH			6

#define OMAP3430_CLKTRCTRL_CAM_MASK			(0x3 << 0)

#define OMAP3430_ST_MCBSP4_SHIFT			2

#define OMAP3430_ST_MCBSP3_SHIFT			1

#define OMAP3430_ST_MCBSP2_SHIFT			0

#define OMAP3430_CLKSEL_GPT9_MASK			(1 << 7)

#define OMAP3430_CLKSEL_GPT8_MASK			(1 << 6)

#define OMAP3430_CLKSEL_GPT7_MASK			(1 << 5)

#define OMAP3430_CLKSEL_GPT6_MASK			(1 << 4)

#define OMAP3430_CLKSEL_GPT5_MASK			(1 << 3)

#define OMAP3430_CLKSEL_GPT4_MASK			(1 << 2)

#define OMAP3430_CLKSEL_GPT3_MASK			(1 << 1)

#define OMAP3430_CLKSEL_GPT2_MASK			(1 << 0)

#define OMAP3430_CLKTRCTRL_PER_MASK			(0x3 << 0)

#define OMAP3430_DIV_DPLL4_SHIFT			24

#define OMAP3630_DIV_DPLL4_WIDTH			6

#define OMAP3430_DIV_DPLL3_SHIFT			16

#define OMAP3430_DIV_DPLL3_WIDTH			5

#define OMAP3430_CLKSEL_TRACECLK_SHIFT			11

#define OMAP3430_CLKSEL_TRACECLK_WIDTH			3

#define OMAP3430_CLKSEL_PCLK_SHIFT			8

#define OMAP3430_CLKSEL_PCLK_WIDTH			3

#define OMAP3430_CLKSEL_PCLKX2_SHIFT			6

#define OMAP3430_CLKSEL_PCLKX2_WIDTH			2

#define OMAP3430_CLKSEL_ATCLK_SHIFT			4

#define OMAP3430_CLKSEL_ATCLK_WIDTH			2

#define OMAP3430_TRACE_MUX_CTRL_SHIFT			2

#define OMAP3430_TRACE_MUX_CTRL_WIDTH			2

#define OMAP3430_MUX_CTRL_MASK				(0x3 << 0)

#define OMAP3430_CLKTRCTRL_EMU_MASK			(0x3 << 0)

#define OMAP3430_CLKTRCTRL_NEON_MASK			(0x3 << 0)

#define OMAP3430ES2_EN_USBHOST2_SHIFT			1

#define OMAP3430ES2_EN_USBHOST1_SHIFT			0

#define OMAP3430ES2_EN_USBHOST_SHIFT			0

#define OMAP3430ES2_ST_USBHOST_IDLE_SHIFT		1

#define OMAP3430ES2_ST_USBHOST_STDBY_SHIFT		0

#define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK		(3 << 0)

#define OMAP34XX_CLKSTCTRL_DISABLE_AUTO		0x0

#define OMAP34XX_CLKSTCTRL_FORCE_SLEEP		0x1

arch/arm/mach-omap2/omap_hwmod.h

+0 −6
Original line number Diff line number Diff line
@@ -343,11 +343,8 @@ struct omap_hwmod_class_sysconfig { 
/**

 * struct omap_hwmod_omap2_prcm - OMAP2/3-specific PRCM data

 * @module_offs: PRCM submodule offset from the start of the PRM/CM

 * @prcm_reg_id: PRCM register ID (e.g., 3 for CM_AUTOIDLE3)

 * @module_bit: register bit shift for AUTOIDLE, WKST, WKEN, GRPSEL regs

 * @idlest_reg_id: IDLEST register ID (e.g., 3 for CM_IDLEST3)

 * @idlest_idle_bit: register bit shift for CM_IDLEST slave idle bit

 * @idlest_stdby_bit: register bit shift for CM_IDLEST master standby bit

 *

 * @prcm_reg_id and @module_bit are specific to the AUTOIDLE, WKST,

 * WKEN, GRPSEL registers.  In an ideal world, no extra information
@@ -357,11 +354,8 @@ struct omap_hwmod_class_sysconfig { 
 */

struct omap_hwmod_omap2_prcm {

	s16 module_offs;

	u8 prcm_reg_id;

	u8 module_bit;

	u8 idlest_reg_id;

	u8 idlest_idle_bit;

	u8 idlest_stdby_bit;

};



/*

arch/arm/mach-omap2/omap_hwmod_2420_data.c

+0 −14
Original line number Diff line number Diff line
@@ -111,8 +111,6 @@ static struct omap_hwmod omap2420_i2c1_hwmod = { 
	.prcm		= {

		.omap2 = {

			.module_offs = CORE_MOD,

			.prcm_reg_id = 1,

			.module_bit = OMAP2420_EN_I2C1_SHIFT,

			.idlest_reg_id = 1,

			.idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,

		},
@@ -134,8 +132,6 @@ static struct omap_hwmod omap2420_i2c2_hwmod = { 
	.prcm		= {

		.omap2 = {

			.module_offs = CORE_MOD,

			.prcm_reg_id = 1,

			.module_bit = OMAP2420_EN_I2C2_SHIFT,

			.idlest_reg_id = 1,

			.idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,

		},
@@ -167,8 +163,6 @@ static struct omap_hwmod omap2420_mailbox_hwmod = { 
	.main_clk	= "mailboxes_ick",

	.prcm		= {

		.omap2 = {

			.prcm_reg_id = 1,

			.module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,

			.module_offs = CORE_MOD,

			.idlest_reg_id = 1,

			.idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
@@ -197,8 +191,6 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod = { 
	.main_clk	= "mcbsp1_fck",

	.prcm		= {

		.omap2 = {

			.prcm_reg_id = 1,

			.module_bit = OMAP24XX_EN_MCBSP1_SHIFT,

			.module_offs = CORE_MOD,

			.idlest_reg_id = 1,

			.idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
@@ -215,8 +207,6 @@ static struct omap_hwmod omap2420_mcbsp2_hwmod = { 
	.main_clk	= "mcbsp2_fck",

	.prcm		= {

		.omap2 = {

			.prcm_reg_id = 1,

			.module_bit = OMAP24XX_EN_MCBSP2_SHIFT,

			.module_offs = CORE_MOD,

			.idlest_reg_id = 1,

			.idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
@@ -247,8 +237,6 @@ static struct omap_hwmod omap2420_msdi1_hwmod = { 
	.main_clk	= "mmc_fck",

	.prcm		= {

		.omap2 = {

			.prcm_reg_id = 1,

			.module_bit = OMAP2420_EN_MMC_SHIFT,

			.module_offs = CORE_MOD,

			.idlest_reg_id = 1,

			.idlest_idle_bit = OMAP2420_ST_MMC_SHIFT,
@@ -264,8 +252,6 @@ static struct omap_hwmod omap2420_hdq1w_hwmod = { 
	.prcm		= {

		.omap2 = {

			.module_offs = CORE_MOD,

			.prcm_reg_id = 1,

			.module_bit = OMAP24XX_EN_HDQ_SHIFT,

			.idlest_reg_id = 1,

			.idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,

		},

arch/arm/mach-omap2/omap_hwmod_2430_data.c

+0 −28
Original line number Diff line number Diff line
@@ -97,8 +97,6 @@ static struct omap_hwmod omap2430_i2c1_hwmod = { 
			 * to hwmod framework.

			 */

			.module_offs = CORE_MOD,

			.prcm_reg_id = 1,

			.module_bit = OMAP2430_EN_I2CHS1_SHIFT,

			.idlest_reg_id = 1,

			.idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT,

		},
@@ -115,8 +113,6 @@ static struct omap_hwmod omap2430_i2c2_hwmod = { 
	.prcm		= {

		.omap2 = {

			.module_offs = CORE_MOD,

			.prcm_reg_id = 1,

			.module_bit = OMAP2430_EN_I2CHS2_SHIFT,

			.idlest_reg_id = 1,

			.idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT,

		},
@@ -132,8 +128,6 @@ static struct omap_hwmod omap2430_gpio5_hwmod = { 
	.main_clk	= "gpio5_fck",

	.prcm		= {

		.omap2 = {

			.prcm_reg_id = 2,

			.module_bit = OMAP2430_EN_GPIO5_SHIFT,

			.module_offs = CORE_MOD,

			.idlest_reg_id = 2,

			.idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT,
@@ -165,8 +159,6 @@ static struct omap_hwmod omap2430_mailbox_hwmod = { 
	.main_clk	= "mailboxes_ick",

	.prcm		= {

		.omap2 = {

			.prcm_reg_id = 1,

			.module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,

			.module_offs = CORE_MOD,

			.idlest_reg_id = 1,

			.idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
@@ -185,8 +177,6 @@ static struct omap_hwmod omap2430_mcspi3_hwmod = { 
	.prcm		= {

		.omap2 = {

			.module_offs = CORE_MOD,

			.prcm_reg_id = 2,

			.module_bit = OMAP2430_EN_MCSPI3_SHIFT,

			.idlest_reg_id = 2,

			.idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT,

		},
@@ -219,8 +209,6 @@ static struct omap_hwmod omap2430_usbhsotg_hwmod = { 
	.main_clk	= "usbhs_ick",

	.prcm		= {

		.omap2 = {

			.prcm_reg_id = 1,

			.module_bit = OMAP2430_EN_USBHS_MASK,

			.module_offs = CORE_MOD,

			.idlest_reg_id = 1,

			.idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT,
@@ -266,8 +254,6 @@ static struct omap_hwmod omap2430_mcbsp1_hwmod = { 
	.main_clk	= "mcbsp1_fck",

	.prcm		= {

		.omap2 = {

			.prcm_reg_id = 1,

			.module_bit = OMAP24XX_EN_MCBSP1_SHIFT,

			.module_offs = CORE_MOD,

			.idlest_reg_id = 1,

			.idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
@@ -284,8 +270,6 @@ static struct omap_hwmod omap2430_mcbsp2_hwmod = { 
	.main_clk	= "mcbsp2_fck",

	.prcm		= {

		.omap2 = {

			.prcm_reg_id = 1,

			.module_bit = OMAP24XX_EN_MCBSP2_SHIFT,

			.module_offs = CORE_MOD,

			.idlest_reg_id = 1,

			.idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
@@ -302,8 +286,6 @@ static struct omap_hwmod omap2430_mcbsp3_hwmod = { 
	.main_clk	= "mcbsp3_fck",

	.prcm		= {

		.omap2 = {

			.prcm_reg_id = 1,

			.module_bit = OMAP2430_EN_MCBSP3_SHIFT,

			.module_offs = CORE_MOD,

			.idlest_reg_id = 2,

			.idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT,
@@ -320,8 +302,6 @@ static struct omap_hwmod omap2430_mcbsp4_hwmod = { 
	.main_clk	= "mcbsp4_fck",

	.prcm		= {

		.omap2 = {

			.prcm_reg_id = 1,

			.module_bit = OMAP2430_EN_MCBSP4_SHIFT,

			.module_offs = CORE_MOD,

			.idlest_reg_id = 2,

			.idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT,
@@ -338,8 +318,6 @@ static struct omap_hwmod omap2430_mcbsp5_hwmod = { 
	.main_clk	= "mcbsp5_fck",

	.prcm		= {

		.omap2 = {

			.prcm_reg_id = 1,

			.module_bit = OMAP2430_EN_MCBSP5_SHIFT,

			.module_offs = CORE_MOD,

			.idlest_reg_id = 2,

			.idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT,
@@ -384,8 +362,6 @@ static struct omap_hwmod omap2430_mmc1_hwmod = { 
	.prcm		= {

		.omap2 = {

			.module_offs = CORE_MOD,

			.prcm_reg_id = 2,

			.module_bit  = OMAP2430_EN_MMCHS1_SHIFT,

			.idlest_reg_id = 2,

			.idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT,

		},
@@ -408,8 +384,6 @@ static struct omap_hwmod omap2430_mmc2_hwmod = { 
	.prcm		= {

		.omap2 = {

			.module_offs = CORE_MOD,

			.prcm_reg_id = 2,

			.module_bit  = OMAP2430_EN_MMCHS2_SHIFT,

			.idlest_reg_id = 2,

			.idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT,

		},
@@ -424,8 +398,6 @@ static struct omap_hwmod omap2430_hdq1w_hwmod = { 
	.prcm		= {

		.omap2 = {

			.module_offs = CORE_MOD,

			.prcm_reg_id = 1,

			.module_bit = OMAP24XX_EN_HDQ_SHIFT,

			.idlest_reg_id = 1,

			.idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,

		},

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