Commit a7c5047d authored by Eric Anholt's avatar Eric Anholt
Browse files

drm/vc4: Fix setting of vertical timings in the CRTC. 



It looks like when I went to add the interlaced bits, I just took the
existing PV_VERT* block and indented it, instead of copy and pasting
it first.  Without this, changing resolution never worked.

Signed-off-by: default avatarEric Anholt <eric@anholt.net>
parent c31806fb

drivers/gpu/drm/vc4/vc4_crtc.c

+10 −0
Original line number Original line Diff line number Diff line
@@ -212,6 +212,16 @@ static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc) 
				 PV_HORZB_HFP) |

				 PV_HORZB_HFP) |

		   VC4_SET_FIELD(mode->hdisplay, PV_HORZB_HACTIVE));

		   VC4_SET_FIELD(mode->hdisplay, PV_HORZB_HACTIVE));





	CRTC_WRITE(PV_VERTA,

		   VC4_SET_FIELD(mode->vtotal - mode->vsync_end,

				 PV_VERTA_VBP) |

		   VC4_SET_FIELD(mode->vsync_end - mode->vsync_start,

				 PV_VERTA_VSYNC));

	CRTC_WRITE(PV_VERTB,

		   VC4_SET_FIELD(mode->vsync_start - mode->vdisplay,

				 PV_VERTB_VFP) |

		   VC4_SET_FIELD(vactive, PV_VERTB_VACTIVE));



	if (interlace) {

	if (interlace) {

		CRTC_WRITE(PV_VERTA_EVEN,

		CRTC_WRITE(PV_VERTA_EVEN,

			   VC4_SET_FIELD(mode->vtotal - mode->vsync_end - 1,

			   VC4_SET_FIELD(mode->vtotal - mode->vsync_end - 1,

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