Commit a7ac1cfa authored by Zhenyu Ye's avatar Zhenyu Ye Committed by Catalin Marinas
Browse files

arm64: tlb: Set the TTL field in flush_*_tlb_range 



This patch implement flush_{pmd|pud}_tlb_range() in arm64 by
calling __flush_tlb_range() with the corresponding stride and
tlb_level values.

Signed-off-by: default avatarZhenyu Ye <yezhenyu2@huawei.com>
Link: https://lore.kernel.org/r/20200625080314.230-7-yezhenyu2@huawei.com


Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent c4ab2cbc

arch/arm64/include/asm/pgtable.h

+10 −0
Original line number Diff line number Diff line
@@ -40,6 +40,16 @@ extern void __pmd_error(const char *file, int line, unsigned long val); 
extern void __pud_error(const char *file, int line, unsigned long val);

extern void __pgd_error(const char *file, int line, unsigned long val);



#ifdef CONFIG_TRANSPARENT_HUGEPAGE

#define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE



/* Set stride and tlb_level in flush_*_tlb_range */

#define flush_pmd_tlb_range(vma, addr, end)	\

	__flush_tlb_range(vma, addr, end, PMD_SIZE, false, 2)

#define flush_pud_tlb_range(vma, addr, end)	\

	__flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1)

#endif /* CONFIG_TRANSPARENT_HUGEPAGE */



/*

 * ZERO_PAGE is a global shared page that is always zero: used

 * for zero-mapped memory areas etc..

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