Commit a7a7a0e6 authored by Michel Thierry's avatar Michel Thierry Committed by Lucas De Marchi
Browse files

drm/i915/tgl: Tigerlake only has global MOCS registers 



Until Icelake, each engine had its own set of 64 MOCS registers. In
order to simplify, Tigerlake moves to only 64 Global MOCS registers,
which are no longer part of the engine context. Since these registers
are now global, they also only need to be initialized once.

>From Gen12 onwards, MOCS must specify the target cache (3:2) and LRU
management (5:4) fields and cannot be programmed to 'use the value from
Private PAT', because these fields are no longer part of the PPAT. Also
cacheability control (1:0) field has changed, 00 no longer means 'use
controls from page table', but uncacheable (UC).

v2 (Lucas):
    - Move the changes to the fault registers to a separate commit - the
      old ones overlap with the range used by the new global MOCS
      (requested by Daniele)
v3 (Lucas):
    - Clarify comment about setting the unused entries to the same value
      of index 0, that is the invalid entry (requested by Daniele)
    - Move changes to DONE_REG and ERROR_GEN6 to a separate commit
      (requested by Daniele)

Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: default avatarMichel Thierry <michel.thierry@intel.com>
Signed-off-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: default avatarTomasz Lis <tomasz.lis@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190730180407.5993-5-lucas.demarchi@intel.com
parent 2ddf9921

drivers/gpu/drm/i915/gt/intel_mocs.c

+43 −1
Original line number Diff line number Diff line
@@ -392,6 +392,10 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine) 
	unsigned int index;

	u32 unused_value;



	/* Platforms with global MOCS do not need per-engine initialization. */

	if (HAS_GLOBAL_MOCS_REGISTERS(gt->i915))

		return;



	/* Called under a blanket forcewake */

	assert_forcewakes_active(uncore, FORCEWAKE_ALL);
@@ -416,6 +420,43 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine) 
				      unused_value);

}



/**

 * intel_mocs_init_global() - program the global mocs registers

 * gt:      pointer to struct intel_gt

 *

 * This function initializes the MOCS global registers.

 */

void intel_mocs_init_global(struct intel_gt *gt)

{

	struct intel_uncore *uncore = gt->uncore;

	struct drm_i915_mocs_table table;

	unsigned int index;



	if (!HAS_GLOBAL_MOCS_REGISTERS(gt->i915))

		return;



	if (!get_mocs_settings(gt, &table))

		return;



	if (GEM_DEBUG_WARN_ON(table.size > table.n_entries))

		return;



	for (index = 0; index < table.size; index++)

		intel_uncore_write(uncore,

				   GEN12_GLOBAL_MOCS(index),

				   table.table[index].control_value);



	/*

	 * Ok, now set the unused entries to the invalid entry (index 0). These

	 * entries are officially undefined and no contract for the contents and

	 * settings is given for these entries.

	 */

	for (; index < table.n_entries; index++)

		intel_uncore_write(uncore,

				   GEN12_GLOBAL_MOCS(index),

				   table.table[0].control_value);

}



/**

 * emit_mocs_control_table() - emit the mocs control table

 * @rq:	Request to set up the MOCS table for.
@@ -619,7 +660,8 @@ int intel_mocs_emit(struct i915_request *rq) 
	struct drm_i915_mocs_table t;

	int ret;



	if (rq->engine->class != RENDER_CLASS)

	if (HAS_GLOBAL_MOCS_REGISTERS(rq->i915) ||

	    rq->engine->class != RENDER_CLASS)

		return 0;



	if (get_mocs_settings(rq->engine->gt, &t)) {

drivers/gpu/drm/i915/gt/intel_mocs.h

+1 −0
Original line number Diff line number Diff line
@@ -54,6 +54,7 @@ struct intel_engine_cs; 
struct intel_gt;



void intel_mocs_init_l3cc_table(struct intel_gt *gt);

void intel_mocs_init_global(struct intel_gt *gt);

void intel_mocs_init_engine(struct intel_engine_cs *engine);



int intel_mocs_emit(struct i915_request *rq);

drivers/gpu/drm/i915/i915_drv.h

+2 −0
Original line number Diff line number Diff line
@@ -2280,6 +2280,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, 


#define HAS_POOLED_EU(dev_priv)	(INTEL_INFO(dev_priv)->has_pooled_eu)



#define HAS_GLOBAL_MOCS_REGISTERS(dev_priv)	(INTEL_INFO(dev_priv)->has_global_mocs)



#define INTEL_PCH_DEVICE_ID_MASK		0xff80

#define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00

#define INTEL_PCH_CPT_DEVICE_ID_TYPE		0x1c00

drivers/gpu/drm/i915/i915_gem.c

+1 −0
Original line number Diff line number Diff line
@@ -1247,6 +1247,7 @@ int i915_gem_init_hw(struct drm_i915_private *i915) 
		goto out;

	}



	intel_mocs_init_global(gt);

	intel_mocs_init_l3cc_table(gt);



	intel_engines_set_scheduler_caps(i915);

drivers/gpu/drm/i915/i915_pci.c

+2 −1
Original line number Diff line number Diff line
@@ -783,7 +783,8 @@ static const struct intel_device_info intel_elkhartlake_info = { 
		[TRANSCODER_D] = TRANSCODER_D_OFFSET, \

		[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \

		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \

	}

	}, \

	.has_global_mocs = 1



static const struct intel_device_info intel_tigerlake_12_info = {

	GEN12_FEATURES,

CRA Git | Maintained and supported by SUSTech CRA and CCSE