Commit a754f708 authored Nov 03, 2007 by Ralf Baechle

[MIPS] Sibyte: resurrect old cache hack.



The recent switch of the Sibyte SOCs from the processor specific cache
managment code in c-sb1.c to c-r4k.c lost this old hack

    [MIPS] Hack for SB1 cache issues

    Removing flush_icache_page a while ago broke SB1 which was using an empty
    flush_data_cache_page function.  This glues things well enough so a more
    efficient but also more intrusive solution can be found later.

    Signed-Off-By: Thiemo Seufer <ths@networkno.de>
    Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

in the hope it was no longer needed.  As it turns it still is so resurrect
it until there is a better solution.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

parent 99fee6d7

arch/mips/mm/c-r4k.c

+6 −1

Original line number	Diff line number	Diff line
		@@ -7,6 +7,7 @@
		* Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
		* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
		*/
		#include <linux/hardirq.h>
		#include <linux/init.h>
		#include <linux/highmem.h>
		#include <linux/kernel.h>
		@@ -507,7 +508,11 @@ static inline void local_r4k_flush_data_cache_page(void * addr)

		static void r4k_flush_data_cache_page(unsigned long addr)
		{
		r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr, 1, 1);
		if (in_atomic())
		local_r4k_flush_data_cache_page((void *)addr);
		else
		r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr,
		1, 1);
		}

		struct flush_icache_range_args {

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