Commit a71e5529 authored by Aric Cyr's avatar Aric Cyr Committed by Alex Deucher
Browse files

drm/amd/display: Multi-display underflow observed 



[Why]
FP2 programming not happening when topology changes occur with multiple
displays.

[How]
Ensure FP2 is programmed whenever global sync changes occur but wait for
VACTIVE first to avoid underflow.

Signed-off-by: default avatarAric Cyr <aric.cyr@amd.com>
Acked-by: default avatarBindu Ramamurthy <bindu.r@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent cbac53f7

drivers/gpu/drm/amd/display/dc/core/dc.c

+0 −20
Original line number Diff line number Diff line
@@ -2625,26 +2625,6 @@ static void commit_planes_for_stream(struct dc *dc, 
		}

	}



	if (update_type != UPDATE_TYPE_FAST) {

		// If changing VTG FP2: wait until back in vactive to program FP2

		// Need to ensure that pipe unlock happens soon after to minimize race condition

		for (i = 0; i < dc->res_pool->pipe_count; i++) {

			struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];



			if (pipe_ctx->top_pipe || pipe_ctx->stream != stream)

				continue;



			if (!pipe_ctx->update_flags.bits.global_sync)

				continue;



			pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK);

			pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);



			pipe_ctx->stream_res.tg->funcs->set_vtg_params(

					pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true);

		}

	}



	if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock)

		dc->hwss.interdependent_update_lock(dc, context, false);

	else

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

+9 −3
Original line number Diff line number Diff line
@@ -1586,7 +1586,10 @@ static void dcn20_program_pipe( 
			&& !pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe)

		hws->funcs.blank_pixel_data(dc, pipe_ctx, !pipe_ctx->plane_state->visible);



	if (pipe_ctx->update_flags.bits.global_sync) {

	/* Only update TG on top pipe */

	if (pipe_ctx->update_flags.bits.global_sync && !pipe_ctx->top_pipe

			&& !pipe_ctx->prev_odm_pipe) {



		pipe_ctx->stream_res.tg->funcs->program_global_sync(

				pipe_ctx->stream_res.tg,

				pipe_ctx->pipe_dlg_param.vready_offset,
@@ -1594,8 +1597,11 @@ static void dcn20_program_pipe( 
				pipe_ctx->pipe_dlg_param.vupdate_offset,

				pipe_ctx->pipe_dlg_param.vupdate_width);



		pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK);

		pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);



		pipe_ctx->stream_res.tg->funcs->set_vtg_params(

				pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, false);

				pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true);



		if (hws->funcs.setup_vupdate_interrupt)

			hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);

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