Commit a714dceb authored May 07, 2018 by Sekhar Nori Committed by Stephen Boyd May 15, 2018

clk: davinci: psc-da830: fix USB0 48MHz PHY clock registration



USB0 48MHz PHY clock registration fails on DA830 because the
da8xx-cfgchip clock driver cannot get a reference to USB0
LPSC clock.

The USB0 LPSC needs to be enabled during PHY clock enable. Setup
the clock lookup correctly to fix this.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

parent 60cc43fc

drivers/clk/davinci/psc-da830.c

+2 −1

Original line number	Diff line number	Diff line
		@@ -55,7 +55,8 @@ const struct davinci_psc_init_data da830_psc0_init_data = {
		.psc_init = &da830_psc0_init,
		};

		LPSC_CLKDEV2(usb0_clkdev, NULL, "musb-da8xx",
		LPSC_CLKDEV3(usb0_clkdev, "fck", "da830-usb-phy-clks",
		NULL, "musb-da8xx",
		NULL, "cppi41-dmaengine");
		LPSC_CLKDEV1(usb1_clkdev, NULL, "ohci-da8xx");
		/* REVISIT: gpio-davinci.c should be modified to drop con_id */

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