Commit a6dc3cd7 authored by Suzuki K Poulose's avatar Suzuki K Poulose Committed by Will Deacon
Browse files

arm64: cpufeature: Check availability of AArch32 



On ARMv8 support for AArch32 state is optional. Hence it is
not safe to check the AArch32 ID registers for sanity, which
could lead to false warnings. This patch makes sure that the
AArch32 state is implemented before we keep track of the 32bit
ID registers.

As per ARM ARM (D.1.21.2 - Support for Exception Levels and
Execution States, DDI0487A.h), checking the support for AArch32
at EL0 is good enough to check the support for AArch32 (i.e,
AArch32 at EL1 => AArch32 at EL0, but not vice versa).

Tested-by: default avatarYury Norov <ynorov@caviumnetworks.com>
Signed-off-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent c80aba80

arch/arm64/kernel/cpufeature.c

+47 −39
Original line number Diff line number Diff line
@@ -439,6 +439,8 @@ void __init init_cpu_features(struct cpuinfo_arm64 *info) 
	init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);

	init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);

	init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);



	if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {

		init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);

		init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);

		init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
@@ -457,6 +459,8 @@ void __init init_cpu_features(struct cpuinfo_arm64 *info) 
		init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);

	}



}



static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)

{

	struct arm64_ftr_bits *ftrp;
@@ -559,9 +563,12 @@ void update_cpu_features(int cpu, 
				      info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);



	/*

	 * If we have AArch32, we care about 32-bit features for compat. These

	 * registers should be RES0 otherwise.

	 * If we have AArch32, we care about 32-bit features for compat.

	 * If the system doesn't support AArch32, don't update them.

	 */

	if (id_aa64pfr0_32bit_el0(read_system_reg(SYS_ID_AA64PFR0_EL1)) &&

		id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {



		taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,

					info->reg_id_dfr0, boot->reg_id_dfr0);

		taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
@@ -600,6 +607,7 @@ void update_cpu_features(int cpu, 
					info->reg_mvfr1, boot->reg_mvfr1);

		taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,

					info->reg_mvfr2, boot->reg_mvfr2);

	}



	/*

	 * Mismatched CPU features are a recipe for disaster. Don't even

arch/arm64/kernel/cpuinfo.c

+20 −17
Original line number Diff line number Diff line
@@ -216,6 +216,8 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info) 
	info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1);

	info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1);



	/* Update the 32bit ID registers only if AArch32 is implemented */

	if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {

		info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1);

		info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1);

		info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1);
@@ -233,6 +235,7 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info) 
		info->reg_mvfr0 = read_cpuid(MVFR0_EL1);

		info->reg_mvfr1 = read_cpuid(MVFR1_EL1);

		info->reg_mvfr2 = read_cpuid(MVFR2_EL1);

	}



	cpuinfo_detect_icache_policy(info);

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