mt76: move mt76x02_beacon_offset in mt76x02_util.c (a6daf796) · Commits · 戴 / test

drivers/net/wireless/mediatek/mt76/mt76x0/init.c

+1 −27

Original line number	Diff line number	Diff line
		@@ -168,30 +168,13 @@ static int mt76x0_init_bbp(struct mt76x0_dev *dev)
		return 0;
		}

		static void
		mt76_init_beacon_offsets(struct mt76x0_dev *dev)
		{
		u16 base = MT_BEACON_BASE;
		u32 regs[4] = {};
		int i;

		for (i = 0; i < 16; i++) {
		u16 addr = dev->beacon_offsets[i];

		regs[i / 4] \|= ((addr - base) / 64) << (8 * (i % 4));
		}

		for (i = 0; i < 4; i++)
		mt76_wr(dev, MT_BCN_OFFSET(i), regs[i]);
		}

		static void mt76x0_init_mac_registers(struct mt76x0_dev *dev)
		{
		u32 reg;

		RANDOM_WRITE(dev, common_mac_reg_table);

		mt76_init_beacon_offsets(dev);
		mt76x02_set_beacon_offsets(&dev->mt76);

		/* Enable PBF and MAC clock SYS_CTRL[11:10] = 0x3 */
		RANDOM_WRITE(dev, mt76x0_mac_reg_table);
		@@ -372,17 +355,8 @@ EXPORT_SYMBOL_GPL(mt76x0_mac_stop);

		int mt76x0_init_hardware(struct mt76x0_dev *dev)
		{
		static const u16 beacon_offsets[16] = {
		/* 512 byte per beacon */
		0xc000, 0xc200, 0xc400, 0xc600,
		0xc800, 0xca00, 0xcc00, 0xce00,
		0xd000, 0xd200, 0xd400, 0xd600,
		0xd800, 0xda00, 0xdc00, 0xde00
		};
		int ret;

		dev->beacon_offsets = beacon_offsets;

		if (!mt76_poll_msec(dev, MT_WPDMA_GLO_CFG,
		MT_WPDMA_GLO_CFG_TX_DMA_BUSY \|
		MT_WPDMA_GLO_CFG_RX_DMA_BUSY, 0, 100))

+0 −2

Original line number	Diff line number	Diff line
		@@ -87,8 +87,6 @@ struct mt76x0_dev {

		spinlock_t mac_lock;

		const u16 *beacon_offsets;

		struct mt76x0_caldata caldata;

		struct mutex reg_atomic_mutex;

+38 −0

Original line number	Diff line number	Diff line
		@@ -454,4 +454,42 @@ bool mt76x02_tx_status_data(struct mt76_dev dev, u8 update)
		}
		EXPORT_SYMBOL_GPL(mt76x02_tx_status_data);

		const u16 mt76x02_beacon_offsets[16] = {
		/* 1024 byte per beacon */
		0xc000,
		0xc400,
		0xc800,
		0xcc00,
		0xd000,
		0xd400,
		0xd800,
		0xdc00,
		/* BSS idx 8-15 not used for beacons */
		0xc000,
		0xc000,
		0xc000,
		0xc000,
		0xc000,
		0xc000,
		0xc000,
		0xc000,
		};
		EXPORT_SYMBOL_GPL(mt76x02_beacon_offsets);

		void mt76x02_set_beacon_offsets(struct mt76_dev *dev)
		{
		u16 val, base = MT_BEACON_BASE;
		u32 regs[4] = {};
		int i;

		for (i = 0; i < 16; i++) {
		val = mt76x02_beacon_offsets[i] - base;
		regs[i / 4] \|= (val / 64) << (8 * (i % 4));
		}

		for (i = 0; i < 4; i++)
		__mt76_wr(dev, MT_BCN_OFFSET(i), regs[i]);
		}
		EXPORT_SYMBOL_GPL(mt76x02_set_beacon_offsets);

		MODULE_LICENSE("Dual BSD/GPL");

+2 −0

Original line number	Diff line number	Diff line
		@@ -52,6 +52,8 @@ void mt76x02_tx_complete_skb(struct mt76_dev mdev, struct mt76_queue q,
		struct mt76_queue_entry *e, bool flush);
		bool mt76x02_tx_status_data(struct mt76_dev dev, u8 update);

		extern const u16 mt76x02_beacon_offsets[16];
		void mt76x02_set_beacon_offsets(struct mt76_dev *dev);
		void mt76x02_set_irq_mask(struct mt76_dev *dev, u32 clear, u32 set);

		static inline void mt76x02_irq_enable(struct mt76_dev *dev, u32 mask)

+0 −2

Original line number	Diff line number	Diff line
		@@ -78,8 +78,6 @@ struct mt76x2_dev {

		struct mutex mutex;

		const u16 *beacon_offsets;

		u8 txdone_seq;
		DECLARE_KFIFO_PTR(txstatus_fifo, struct mt76x02_tx_status);