Commit a6d74678 authored by Russell King's avatar Russell King
Browse files

ARM: proc-v7: avoid errata 430973 workaround for non-Cortex A8 CPUs 



Avoid the errata 430973 workaround for non-Cortex A8 CPUs.  Having this
workaround enabled introduces an additional branch target buffer flush
into the context switching path, something we wish to avoid.  To allow
this errata to be enabled in multiplatform kernels while reducing its
impact, rearrange the Cortex-A8 CPU support to avoid impacting on other
Version 7 CPUs.

Tested-by: default avatarTony Lindgren <tony@atomide.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent e5a5de44

arch/arm/mm/proc-v7-2level.S

+8 −4
Original line number Diff line number Diff line
@@ -37,15 +37,18 @@ 
 *	It is assumed that:

 *	- we are not using split page tables

 */

ENTRY(cpu_v7_switch_mm)

ENTRY(cpu_ca8_switch_mm)

#ifdef CONFIG_MMU

	mov	r2, #0

	mmid	r1, r1				@ get mm->context.id

	ALT_SMP(orr	r0, r0, #TTB_FLAGS_SMP)

	ALT_UP(orr	r0, r0, #TTB_FLAGS_UP)

#ifdef CONFIG_ARM_ERRATA_430973

	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB

#endif

#endif

ENTRY(cpu_v7_switch_mm)

#ifdef CONFIG_MMU

	mmid	r1, r1				@ get mm->context.id

	ALT_SMP(orr	r0, r0, #TTB_FLAGS_SMP)

	ALT_UP(orr	r0, r0, #TTB_FLAGS_UP)

#ifdef CONFIG_PID_IN_CONTEXTIDR

	mrc	p15, 0, r2, c13, c0, 1		@ read current context ID

	lsr	r2, r2, #8			@ extract the PID
@@ -61,6 +64,7 @@ ENTRY(cpu_v7_switch_mm) 
#endif

	bx	lr

ENDPROC(cpu_v7_switch_mm)

ENDPROC(cpu_ca8_switch_mm)



/*

 *	cpu_v7_set_pte_ext(ptep, pte)

arch/arm/mm/proc-v7.S

+28 −0
Original line number Diff line number Diff line
@@ -152,6 +152,21 @@ ENTRY(cpu_v7_do_resume) 
ENDPROC(cpu_v7_do_resume)

#endif



/*

 * Cortex-A8

 */

	globl_equ	cpu_ca8_proc_init,	cpu_v7_proc_init

	globl_equ	cpu_ca8_proc_fin,	cpu_v7_proc_fin

	globl_equ	cpu_ca8_reset,		cpu_v7_reset

	globl_equ	cpu_ca8_do_idle,	cpu_v7_do_idle

	globl_equ	cpu_ca8_dcache_clean_area, cpu_v7_dcache_clean_area

	globl_equ	cpu_ca8_set_pte_ext,	cpu_v7_set_pte_ext

	globl_equ	cpu_ca8_suspend_size,	cpu_v7_suspend_size

#ifdef CONFIG_ARM_CPU_SUSPEND

	globl_equ	cpu_ca8_do_suspend,	cpu_v7_do_suspend

	globl_equ	cpu_ca8_do_resume,	cpu_v7_do_resume

#endif



/*

 * Cortex-A9 processor functions

 */
@@ -451,7 +466,10 @@ __v7_setup_stack: 


	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)

	define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1

#ifndef CONFIG_ARM_LPAE

	define_processor_functions ca8, dabort=v7_early_abort, pabort=v7_pabort, suspend=1

	define_processor_functions ca9mp, dabort=v7_early_abort, pabort=v7_pabort, suspend=1

#endif

#ifdef CONFIG_CPU_PJ4B

	define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1

#endif
@@ -507,6 +525,16 @@ __v7_ca9mp_proc_info: 
	__v7_proc __v7_ca9mp_proc_info, __v7_ca9mp_setup, proc_fns = ca9mp_processor_functions

	.size	__v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info



	/*

	 * ARM Ltd. Cortex A8 processor.

	 */

	.type	__v7_ca8_proc_info, #object

__v7_ca8_proc_info:

	.long	0x410fc080

	.long	0xff0ffff0

	__v7_proc __v7_ca8_proc_info, __v7_setup, proc_fns = ca8_processor_functions

	.size	__v7_ca8_proc_info, . - __v7_ca8_proc_info



#endif	/* CONFIG_ARM_LPAE */



	/*

CRA Git | Maintained and supported by SUSTech CRA and CCSE