Commit a6a80e1d authored Mar 17, 2009 by Linus Torvalds

Fix potential fast PIT TSC calibration startup glitch

During bootup, when we reprogram the PIT (programmable interval timer)
to start counting down from 0xffff in order to use it for the fast TSC
calibration, we should also make sure to delay a bit afterwards to allow
the PIT hardware to actually start counting with the new value.

That will happens at the next CLK pulse (1.193182 MHz), so the easiest
way to do that is to just wait at least one microsecond after
programming the new PIT counter value. We do that by just reading the
counter value back once - which will take about 2us on PC hardware.

Reported-and-tested-by: john stultz <johnstul@us.ibm.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

parent 19695ec0

arch/x86/kernel/tsc.c

+9 −0

Original line number	Diff line number	Diff line
		@@ -315,6 +315,15 @@ static unsigned long quick_pit_calibrate(void)
		outb(0xff, 0x42);
		outb(0xff, 0x42);

		/*
		* The PIT starts counting at the next edge, so we
		* need to delay for a microsecond. The easiest way
		* to do that is to just read back the 16-bit counter
		* once from the PIT.
		*/
		inb(0x42);
		inb(0x42);

		if (pit_expect_msb(0xff)) {
		int i;
		u64 t1, t2, delta;

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