Commit a6972dec authored by Geert Uytterhoeven's avatar Geert Uytterhoeven Committed by Simon Horman
Browse files

arm64: dts: renesas: r8a77965: Use r8a77965-cpg-mssr binding definitions 



Replace the hardcoded clock indices by R8A77965_CLK_* symbols.

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent 0f6d237c

arch/arm64/boot/dts/renesas/r8a77965.dtsi

+6 −6
Original line number Diff line number Diff line
@@ -737,7 +737,7 @@ 
			reg = <0 0xe6e60000 0 64>;

			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 207>,

				 <&cpg CPG_CORE 20>,

				 <&cpg CPG_CORE R8A77965_CLK_S3D1>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac1 0x51>, <&dmac1 0x50>,
@@ -754,7 +754,7 @@ 
			reg = <0 0xe6e68000 0 64>;

			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 206>,

				 <&cpg CPG_CORE 20>,

				 <&cpg CPG_CORE R8A77965_CLK_S3D1>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac1 0x53>, <&dmac1 0x52>,
@@ -771,7 +771,7 @@ 
			reg = <0 0xe6e88000 0 64>;

			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 310>,

				 <&cpg CPG_CORE 20>,

				 <&cpg CPG_CORE R8A77965_CLK_S3D1>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
@@ -785,7 +785,7 @@ 
			reg = <0 0xe6c50000 0 64>;

			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 204>,

				 <&cpg CPG_CORE 20>,

				 <&cpg CPG_CORE R8A77965_CLK_S3D1>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac0 0x57>, <&dmac0 0x56>;
@@ -801,7 +801,7 @@ 
			reg = <0 0xe6c40000 0 64>;

			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 203>,

				 <&cpg CPG_CORE 20>,

				 <&cpg CPG_CORE R8A77965_CLK_S3D1>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac0 0x59>, <&dmac0 0x58>;
@@ -817,7 +817,7 @@ 
			reg = <0 0xe6f30000 0 64>;

			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 202>,

				 <&cpg CPG_CORE 20>,

				 <&cpg CPG_CORE R8A77965_CLK_S3D1>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,

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