Commit a68a8481 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'hns3-next' 



Huazhong Tan says:

====================
code optimizations & bugfixes for HNS3 driver

This patchset includes bugfixes and code optimizations for the HNS3
ethernet controller driver
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents beb73559 54a395b6

drivers/net/ethernet/hisilicon/hns3/hclge_mbx.h

+3 −1
Original line number Diff line number Diff line
@@ -40,6 +40,8 @@ enum HCLGE_MBX_OPCODE { 
	HCLGE_MBX_SET_ALIVE,		/* (VF -> PF) set alive state */

	HCLGE_MBX_SET_MTU,		/* (VF -> PF) set mtu */

	HCLGE_MBX_GET_QID_IN_PF,	/* (VF -> PF) get queue id in pf */

	HCLGE_MBX_LINK_STAT_MODE,	/* (PF -> VF) link mode has changed */

	HCLGE_MBX_GET_LINK_MODE,	/* (VF -> PF) get the link mode of pf */

};



/* below are per-VF mac-vlan subcodes */
@@ -60,7 +62,7 @@ enum hclge_mbx_vlan_cfg_subcode { 
};



#define HCLGE_MBX_MAX_MSG_SIZE	16

#define HCLGE_MBX_MAX_RESP_DATA_SIZE	8

#define HCLGE_MBX_MAX_RESP_DATA_SIZE	16

#define HCLGE_MBX_RING_MAP_BASIC_MSG_NUM	3

#define HCLGE_MBX_RING_NODE_VARIABLE_NUM	3

drivers/net/ethernet/hisilicon/hns3/hnae3.h

+1 −1
Original line number Diff line number Diff line
@@ -461,7 +461,7 @@ struct hnae3_ae_ops { 
	bool (*get_hw_reset_stat)(struct hnae3_handle *handle);

	bool (*ae_dev_resetting)(struct hnae3_handle *handle);

	unsigned long (*ae_dev_reset_cnt)(struct hnae3_handle *handle);

	int (*set_gro_en)(struct hnae3_handle *handle, int enable);

	int (*set_gro_en)(struct hnae3_handle *handle, bool enable);

	u16 (*get_global_queue_id)(struct hnae3_handle *handle, u16 queue_id);

	void (*set_timer_task)(struct hnae3_handle *handle, bool enable);

	int (*mac_connect_phy)(struct hnae3_handle *handle);

drivers/net/ethernet/hisilicon/hns3/hns3_enet.c

+12 −21
Original line number Diff line number Diff line
@@ -1349,6 +1349,7 @@ static int hns3_nic_set_features(struct net_device *netdev, 
	netdev_features_t changed = netdev->features ^ features;

	struct hns3_nic_priv *priv = netdev_priv(netdev);

	struct hnae3_handle *h = priv->ae_handle;

	bool enable;

	int ret;



	if (changed & (NETIF_F_TSO | NETIF_F_TSO6)) {
@@ -1359,38 +1360,29 @@ static int hns3_nic_set_features(struct net_device *netdev, 
	}



	if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) {

		if (features & NETIF_F_GRO_HW)

			ret = h->ae_algo->ops->set_gro_en(h, true);

		else

			ret = h->ae_algo->ops->set_gro_en(h, false);

		enable = !!(features & NETIF_F_GRO_HW);

		ret = h->ae_algo->ops->set_gro_en(h, enable);

		if (ret)

			return ret;

	}



	if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) &&

	    h->ae_algo->ops->enable_vlan_filter) {

		if (features & NETIF_F_HW_VLAN_CTAG_FILTER)

			h->ae_algo->ops->enable_vlan_filter(h, true);

		else

			h->ae_algo->ops->enable_vlan_filter(h, false);

		enable = !!(features & NETIF_F_HW_VLAN_CTAG_FILTER);

		h->ae_algo->ops->enable_vlan_filter(h, enable);

	}



	if ((changed & NETIF_F_HW_VLAN_CTAG_RX) &&

	    h->ae_algo->ops->enable_hw_strip_rxvtag) {

		if (features & NETIF_F_HW_VLAN_CTAG_RX)

			ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, true);

		else

			ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, false);



		enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);

		ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable);

		if (ret)

			return ret;

	}



	if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) {

		if (features & NETIF_F_NTUPLE)

			h->ae_algo->ops->enable_fd(h, true);

		else

			h->ae_algo->ops->enable_fd(h, false);

		enable = !!(features & NETIF_F_NTUPLE);

		h->ae_algo->ops->enable_fd(h, enable);

	}



	netdev->features = features;
@@ -1937,8 +1929,7 @@ static void hns3_set_default_feature(struct net_device *netdev) 
		NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC;



	if (pdev->revision >= 0x21) {

		netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER |

			NETIF_F_GRO_HW;

		netdev->hw_features |= NETIF_F_GRO_HW;

		netdev->features |= NETIF_F_GRO_HW;



		if (!(h->flags & HNAE3_SUPPORT_VF)) {
@@ -2777,7 +2768,7 @@ static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group) 
	u32 time_passed_ms;

	u16 new_int_gl;



	if (!ring_group->coal.int_gl || !tqp_vector->last_jiffies)

	if (!tqp_vector->last_jiffies)

		return false;



	if (ring_group->total_packets == 0) {
@@ -2880,7 +2871,7 @@ static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector) 
	}



	if (tx_group->coal.gl_adapt_enable) {

		tx_update = hns3_get_new_int_gl(&tqp_vector->tx_group);

		tx_update = hns3_get_new_int_gl(tx_group);

		if (tx_update)

			hns3_set_vector_coalesce_tx_gl(tqp_vector,

						       tx_group->coal.int_gl);

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c

+34 −28
Original line number Diff line number Diff line
@@ -186,6 +186,38 @@ static bool hclge_is_special_opcode(u16 opcode) 
	return false;

}



static int hclge_cmd_check_retval(struct hclge_hw *hw, struct hclge_desc *desc,

				  int num, int ntc)

{

	u16 opcode, desc_ret;

	int handle;

	int retval;



	opcode = le16_to_cpu(desc[0].opcode);

	for (handle = 0; handle < num; handle++) {

		desc[handle] = hw->cmq.csq.desc[ntc];

		ntc++;

		if (ntc >= hw->cmq.csq.desc_num)

			ntc = 0;

	}

	if (likely(!hclge_is_special_opcode(opcode)))

		desc_ret = le16_to_cpu(desc[num - 1].retval);

	else

		desc_ret = le16_to_cpu(desc[0].retval);



	if (desc_ret == HCLGE_CMD_EXEC_SUCCESS)

		retval = 0;

	else if (desc_ret == HCLGE_CMD_NO_AUTH)

		retval = -EPERM;

	else if (desc_ret == HCLGE_CMD_NOT_SUPPORTED)

		retval = -EOPNOTSUPP;

	else

		retval = -EIO;

	hw->cmq.last_status = desc_ret;



	return retval;

}



/**

 * hclge_cmd_send - send command to command queue

 * @hw: pointer to the hw struct
@@ -203,7 +235,6 @@ int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num) 
	u32 timeout = 0;

	int handle = 0;

	int retval = 0;

	u16 opcode, desc_ret;

	int ntc;



	spin_lock_bh(&hw->cmq.csq.lock);
@@ -219,12 +250,11 @@ int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num) 
	 * which will be use for hardware to write back

	 */

	ntc = hw->cmq.csq.next_to_use;

	opcode = le16_to_cpu(desc[0].opcode);

	while (handle < num) {

		desc_to_use = &hw->cmq.csq.desc[hw->cmq.csq.next_to_use];

		*desc_to_use = desc[handle];

		(hw->cmq.csq.next_to_use)++;

		if (hw->cmq.csq.next_to_use == hw->cmq.csq.desc_num)

		if (hw->cmq.csq.next_to_use >= hw->cmq.csq.desc_num)

			hw->cmq.csq.next_to_use = 0;

		handle++;

	}
@@ -250,31 +280,7 @@ int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num) 
	if (!complete) {

		retval = -EAGAIN;

	} else {

		handle = 0;

		while (handle < num) {

			/* Get the result of hardware write back */

			desc_to_use = &hw->cmq.csq.desc[ntc];

			desc[handle] = *desc_to_use;



			if (likely(!hclge_is_special_opcode(opcode)))

				desc_ret = le16_to_cpu(desc[handle].retval);

			else

				desc_ret = le16_to_cpu(desc[0].retval);



			if (desc_ret == HCLGE_CMD_EXEC_SUCCESS)

				retval = 0;

			else if (desc_ret == HCLGE_CMD_NO_AUTH)

				retval = -EPERM;

			else if (desc_ret == HCLGE_CMD_NOT_SUPPORTED)

				retval = -EOPNOTSUPP;

			else

				retval = -EIO;

			hw->cmq.last_status = desc_ret;

			ntc++;

			handle++;

			if (ntc == hw->cmq.csq.desc_num)

				ntc = 0;

		}

		retval = hclge_cmd_check_retval(hw, desc, num, ntc);

	}



	/* Clean the command send queue */

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

+3 −4
Original line number Diff line number Diff line
@@ -312,16 +312,16 @@ struct hclge_ctrl_vector_chain_cmd { 
	u8 rsv;

};



#define HCLGE_TC_NUM		8

#define HCLGE_MAX_TC_NUM		8

#define HCLGE_TC0_PRI_BUF_EN_B	15 /* Bit 15 indicate enable or not */

#define HCLGE_BUF_UNIT_S	7  /* Buf size is united by 128 bytes */

struct hclge_tx_buff_alloc_cmd {

	__le16 tx_pkt_buff[HCLGE_TC_NUM];

	__le16 tx_pkt_buff[HCLGE_MAX_TC_NUM];

	u8 tx_buff_rsv[8];

};



struct hclge_rx_priv_buff_cmd {

	__le16 buf_num[HCLGE_TC_NUM];

	__le16 buf_num[HCLGE_MAX_TC_NUM];

	__le16 shared_buf;

	u8 rsv[6];

};
@@ -367,7 +367,6 @@ struct hclge_priv_buf { 
	u32 enable;	/* Enable TC private buffer or not */

};



#define HCLGE_MAX_TC_NUM	8

struct hclge_shared_buf {

	struct hclge_waterline self;

	struct hclge_tc_thrd tc_thrd[HCLGE_MAX_TC_NUM];

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