Commit a6822483 authored by Fabien Parent's avatar Fabien Parent Committed by Stephen Boyd
Browse files

clk: mediatek: Add MT8167 clock support 



Add the following clock support for MT8167 SoC: topckgen, apmixedsys,
infracfg, audsys, imgsys, mfgcfg, vdecsys.

Signed-off-by: default avatarFabien Parent <fparent@baylibre.com>
Link: https://lore.kernel.org/r/20200918132303.2831815-2-fparent@baylibre.com


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 8adea9b9

drivers/clk/mediatek/Kconfig

+48 −0
Original line number Diff line number Diff line
@@ -352,6 +352,54 @@ config COMMON_CLK_MT8135 
	help

	  This driver supports MediaTek MT8135 clocks.



config COMMON_CLK_MT8167

	bool "Clock driver for MediaTek MT8167"

	depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST

	select COMMON_CLK_MEDIATEK

	default ARCH_MEDIATEK

	help

	  This driver supports MediaTek MT8167 basic clocks.



config COMMON_CLK_MT8167_AUDSYS

	bool "Clock driver for MediaTek MT8167 audsys"

	depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST

	select COMMON_CLK_MEDIATEK

	default ARCH_MEDIATEK

	help

	  This driver supports MediaTek MT8167 audsys clocks.



config COMMON_CLK_MT8167_IMGSYS

	bool "Clock driver for MediaTek MT8167 imgsys"

	depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST

	select COMMON_CLK_MEDIATEK

	default ARCH_MEDIATEK

	help

	  This driver supports MediaTek MT8167 imgsys clocks.



config COMMON_CLK_MT8167_MFGCFG

	bool "Clock driver for MediaTek MT8167 mfgcfg"

	depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST

	select COMMON_CLK_MEDIATEK

	default ARCH_MEDIATEK

	help

	  This driver supports MediaTek MT8167 mfgcfg clocks.



config COMMON_CLK_MT8167_MMSYS

	bool "Clock driver for MediaTek MT8167 mmsys"

	depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST

	select COMMON_CLK_MEDIATEK

	default ARCH_MEDIATEK

	help

	  This driver supports MediaTek MT8167 mmsys clocks.



config COMMON_CLK_MT8167_VDECSYS

	bool "Clock driver for MediaTek MT8167 vdecsys"

	depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST

	select COMMON_CLK_MEDIATEK

	default ARCH_MEDIATEK

	help

	  This driver supports MediaTek MT8167 vdecsys clocks.



config COMMON_CLK_MT8173

	bool "Clock driver for MediaTek MT8173"

	depends on ARCH_MEDIATEK || COMPILE_TEST

drivers/clk/mediatek/Makefile

+6 −0
Original line number Diff line number Diff line
@@ -47,6 +47,12 @@ obj-$(CONFIG_COMMON_CLK_MT7629) += clk-mt7629.o 
obj-$(CONFIG_COMMON_CLK_MT7629_ETHSYS) += clk-mt7629-eth.o

obj-$(CONFIG_COMMON_CLK_MT7629_HIFSYS) += clk-mt7629-hif.o

obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o

obj-$(CONFIG_COMMON_CLK_MT8167) += clk-mt8167.o

obj-$(CONFIG_COMMON_CLK_MT8167_AUDSYS) += clk-mt8167-aud.o

obj-$(CONFIG_COMMON_CLK_MT8167_IMGSYS) += clk-mt8167-img.o

obj-$(CONFIG_COMMON_CLK_MT8167_MFGCFG) += clk-mt8167-mfgcfg.o

obj-$(CONFIG_COMMON_CLK_MT8167_MMSYS) += clk-mt8167-mm.o

obj-$(CONFIG_COMMON_CLK_MT8167_VDECSYS) += clk-mt8167-vdec.o

obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o

obj-$(CONFIG_COMMON_CLK_MT8173_MMSYS) += clk-mt8173-mm.o

obj-$(CONFIG_COMMON_CLK_MT8183) += clk-mt8183.o

drivers/clk/mediatek/clk-mt8167-aud.c

0 → 100644
+66 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright (c) 2020 MediaTek Inc.

 * Copyright (c) 2020 BayLibre, SAS

 * Author: James Liao <jamesjj.liao@mediatek.com>

 *         Fabien Parent <fparent@baylibre.com>

 */



#include <linux/clk-provider.h>

#include <linux/of.h>

#include <linux/of_address.h>

#include <linux/of_device.h>

#include <linux/platform_device.h>



#include "clk-mtk.h"

#include "clk-gate.h"



#include <dt-bindings/clock/mt8167-clk.h>



static const struct mtk_gate_regs aud_cg_regs = {

	.set_ofs = 0x0,

	.clr_ofs = 0x0,

	.sta_ofs = 0x0,

};



#define GATE_AUD(_id, _name, _parent, _shift) {	\

		.id = _id,			\

		.name = _name,			\

		.parent_name = _parent,		\

		.regs = &aud_cg_regs,		\

		.shift = _shift,		\

		.ops = &mtk_clk_gate_ops_no_setclr,		\

	}



static const struct mtk_gate aud_clks[] __initconst = {

	GATE_AUD(CLK_AUD_AFE, "aud_afe", "clk26m_ck", 2),

	GATE_AUD(CLK_AUD_I2S, "aud_i2s", "i2s_infra_bck", 6),

	GATE_AUD(CLK_AUD_22M, "aud_22m", "rg_aud_engen1", 8),

	GATE_AUD(CLK_AUD_24M, "aud_24m", "rg_aud_engen2", 9),

	GATE_AUD(CLK_AUD_INTDIR, "aud_intdir", "rg_aud_spdif_in", 15),

	GATE_AUD(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner", "rg_aud_engen2", 18),

	GATE_AUD(CLK_AUD_APLL_TUNER, "aud_apll_tuner", "rg_aud_engen1", 19),

	GATE_AUD(CLK_AUD_HDMI, "aud_hdmi", "apll12_div4", 20),

	GATE_AUD(CLK_AUD_SPDF, "aud_spdf", "apll12_div6", 21),

	GATE_AUD(CLK_AUD_ADC, "aud_adc", "aud_afe", 24),

	GATE_AUD(CLK_AUD_DAC, "aud_dac", "aud_afe", 25),

	GATE_AUD(CLK_AUD_DAC_PREDIS, "aud_dac_predis", "aud_afe", 26),

	GATE_AUD(CLK_AUD_TML, "aud_tml", "aud_afe", 27),

};



static void __init mtk_audsys_init(struct device_node *node)

{

	struct clk_onecell_data *clk_data;

	int r;



	clk_data = mtk_alloc_clk_data(CLK_AUD_NR_CLK);



	mtk_clk_register_gates(node, aud_clks, ARRAY_SIZE(aud_clks), clk_data);



	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);

	if (r)

		pr_err("%s(): could not register clock provider: %d\n",

			__func__, r);



}

CLK_OF_DECLARE(mtk_audsys, "mediatek,mt8167-audsys", mtk_audsys_init);

drivers/clk/mediatek/clk-mt8167-img.c

0 → 100644
+60 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright (c) 2020 MediaTek Inc.

 * Copyright (c) 2020 BayLibre, SAS

 * Author: James Liao <jamesjj.liao@mediatek.com>

 *         Fabien Parent <fparent@baylibre.com>

 */



#include <linux/clk-provider.h>

#include <linux/of.h>

#include <linux/of_address.h>

#include <linux/of_device.h>

#include <linux/platform_device.h>



#include "clk-mtk.h"

#include "clk-gate.h"



#include <dt-bindings/clock/mt8167-clk.h>



static const struct mtk_gate_regs img_cg_regs = {

	.set_ofs = 0x4,

	.clr_ofs = 0x8,

	.sta_ofs = 0x0,

};



#define GATE_IMG(_id, _name, _parent, _shift) {		\

		.id = _id,				\

		.name = _name,				\

		.parent_name = _parent,			\

		.regs = &img_cg_regs,			\

		.shift = _shift,			\

		.ops = &mtk_clk_gate_ops_setclr,	\

	}



static const struct mtk_gate img_clks[] __initconst = {

	GATE_IMG(CLK_IMG_LARB1_SMI, "img_larb1_smi", "smi_mm", 0),

	GATE_IMG(CLK_IMG_CAM_SMI, "img_cam_smi", "smi_mm", 5),

	GATE_IMG(CLK_IMG_CAM_CAM, "img_cam_cam", "smi_mm", 6),

	GATE_IMG(CLK_IMG_SEN_TG, "img_sen_tg", "cam_mm", 7),

	GATE_IMG(CLK_IMG_SEN_CAM, "img_sen_cam", "smi_mm", 8),

	GATE_IMG(CLK_IMG_VENC, "img_venc", "smi_mm", 9),

};



static void __init mtk_imgsys_init(struct device_node *node)

{

	struct clk_onecell_data *clk_data;

	int r;



	clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK);



	mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks), clk_data);



	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);



	if (r)

		pr_err("%s(): could not register clock provider: %d\n",

			__func__, r);



}

CLK_OF_DECLARE(mtk_imgsys, "mediatek,mt8167-imgsys", mtk_imgsys_init);

drivers/clk/mediatek/clk-mt8167-mfgcfg.c

0 → 100644
+58 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright (c) 2020 MediaTek Inc.

 * Copyright (c) 2020 BayLibre, SAS

 * Author: James Liao <jamesjj.liao@mediatek.com>

 *         Fabien Parent <fparent@baylibre.com>

 */



#include <linux/clk-provider.h>

#include <linux/of.h>

#include <linux/of_address.h>

#include <linux/of_device.h>

#include <linux/platform_device.h>



#include "clk-mtk.h"

#include "clk-gate.h"



#include <dt-bindings/clock/mt8167-clk.h>



static const struct mtk_gate_regs mfg_cg_regs = {

	.set_ofs = 0x4,

	.clr_ofs = 0x8,

	.sta_ofs = 0x0,

};



#define GATE_MFG(_id, _name, _parent, _shift) {		\

		.id = _id,				\

		.name = _name,				\

		.parent_name = _parent,			\

		.regs = &mfg_cg_regs,			\

		.shift = _shift,			\

		.ops = &mtk_clk_gate_ops_setclr,	\

	}



static const struct mtk_gate mfg_clks[] __initconst = {

	GATE_MFG(CLK_MFG_BAXI, "mfg_baxi", "ahb_infra_sel", 0),

	GATE_MFG(CLK_MFG_BMEM, "mfg_bmem", "gfmux_emi1x_sel", 1),

	GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_mm", 2),

	GATE_MFG(CLK_MFG_B26M, "mfg_b26m", "clk26m_ck", 3),

};



static void __init mtk_mfgcfg_init(struct device_node *node)

{

	struct clk_onecell_data *clk_data;

	int r;



	clk_data = mtk_alloc_clk_data(CLK_MFG_NR_CLK);



	mtk_clk_register_gates(node, mfg_clks, ARRAY_SIZE(mfg_clks), clk_data);



	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);



	if (r)

		pr_err("%s(): could not register clock provider: %d\n",

			__func__, r);



}

CLK_OF_DECLARE(mtk_mfgcfg, "mediatek,mt8167-mfgcfg", mtk_mfgcfg_init);

CRA Git | Maintained and supported by SUSTech CRA and CCSE