Commit a672e99b authored by Will Deacon's avatar Will Deacon Committed by Russell King
Browse files

ARM: 6389/1: errata: incorrect hazard handling in the SCU may lead to data corruption 



On the r2p0, r2p1 and r2p2 versions of the Cortex-A9, data corruption
can occur if a shared cache line is replaced on one CPU as another CPU
is accessing it.

This workaround sets two bits in the diagnostic register of the Cortex-A9,
reducing the linefill issuing capabilities of the processor and
avoiding the erroneous behaviour.

Acked-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 9f05027c

arch/arm/Kconfig

+14 −0
Original line number Original line Diff line number Diff line
@@ -1063,6 +1063,20 @@ config ARM_ERRATA_742230 
	  instruction to behave as a DSB, ensuring the correct behaviour of

	  instruction to behave as a DSB, ensuring the correct behaviour of

	  the two writes.

	  the two writes.





config ARM_ERRATA_742231

	bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"

	depends on CPU_V7 && SMP

	help

	  This option enables the workaround for the 742231 Cortex-A9

	  (r2p0..r2p2) erratum. Under certain conditions, specific to the

	  Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,

	  accessing some data located in the same cache line, may get corrupted

	  data due to bad handling of the address hazard when the line gets

	  replaced from one of the CPUs at the same time as another CPU is

	  accessing it. This workaround sets specific bits in the diagnostic

	  register of the Cortex-A9 which reduces the linefill issuing

	  capabilities of the processor.



config PL310_ERRATA_588369

config PL310_ERRATA_588369

	bool "Clean & Invalidate maintenance operations do not invalidate clean lines"

	bool "Clean & Invalidate maintenance operations do not invalidate clean lines"

	depends on CACHE_L2X0 && ARCH_OMAP4

	depends on CACHE_L2X0 && ARCH_OMAP4

arch/arm/mm/proc-v7.S

+9 −0
Original line number Original line Diff line number Diff line
@@ -243,6 +243,15 @@ __v7_setup: 
	orrle	r10, r10, #1 << 4		@ set bit #4

	orrle	r10, r10, #1 << 4		@ set bit #4

	mcrle	p15, 0, r10, c15, c0, 1		@ write diagnostic register

	mcrle	p15, 0, r10, c15, c0, 1		@ write diagnostic register

#endif

#endif

#ifdef CONFIG_ARM_ERRATA_742231

	teq	r6, #0x20			@ present in r2p0

	teqne	r6, #0x21			@ present in r2p1

	teqne	r6, #0x22			@ present in r2p2

	mrceq	p15, 0, r10, c15, c0, 1		@ read diagnostic register

	orreq	r10, r10, #1 << 12		@ set bit #12

	orreq	r10, r10, #1 << 22		@ set bit #22

	mcreq	p15, 0, r10, c15, c0, 1		@ write diagnostic register

#endif





3:	mov	r10, #0

3:	mov	r10, #0

#ifdef HARVARD_CACHE

#ifdef HARVARD_CACHE

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