Commit a670be33 authored by Dhinakaran Pandiyan's avatar Dhinakaran Pandiyan
Browse files

drm/i915: Move VIDEO_DIP_CTL definitions to their right place. 



The bits weren't defined in descending order.
v2: Move definitions in a separate patch (Manasi)

Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: default avatarDhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: default avatarManasi Navare <manasi.d.navare@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181005185643.31660-2-dhinakaran.pandiyan@intel.com
parent 09209662

drivers/gpu/drm/i915/i915_reg.h

+9 −10
Original line number Diff line number Diff line
@@ -4564,13 +4564,6 @@ enum { 
#define   VIDEO_DIP_FREQ_2VSYNC		(2 << 16)

#define   VIDEO_DIP_FREQ_MASK		(3 << 16)

/* HSW and later: */

#define   VIDEO_DIP_ENABLE_VSC_HSW	(1 << 20)

#define   VIDEO_DIP_ENABLE_GCP_HSW	(1 << 16)

#define   VIDEO_DIP_ENABLE_AVI_HSW	(1 << 12)

#define   VIDEO_DIP_ENABLE_VS_HSW	(1 << 8)

#define   VIDEO_DIP_ENABLE_GMP_HSW	(1 << 4)

#define   VIDEO_DIP_ENABLE_SPD_HSW	(1 << 0)



#define   DRM_DIP_ENABLE		(1 << 28)

#define   PSR_VSC_BIT_7_SET		(1 << 27)

#define   VSC_SELECT_MASK		(0x3 << 25)
@@ -4580,6 +4573,12 @@ enum { 
#define   VSC_DIP_HW_DATA_SW_HEA	(2 << 25)

#define   VSC_DIP_SW_HEA_DATA		(3 << 25)

#define   VDIP_ENABLE_PPS		(1 << 24)

#define   VIDEO_DIP_ENABLE_VSC_HSW	(1 << 20)

#define   VIDEO_DIP_ENABLE_GCP_HSW	(1 << 16)

#define   VIDEO_DIP_ENABLE_AVI_HSW	(1 << 12)

#define   VIDEO_DIP_ENABLE_VS_HSW	(1 << 8)

#define   VIDEO_DIP_ENABLE_GMP_HSW	(1 << 4)

#define   VIDEO_DIP_ENABLE_SPD_HSW	(1 << 0)



/* Panel power sequencing */

#define PPS_BASE			0x61200

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