Commit a66d186c authored by hersen wu's avatar hersen wu Committed by Alex Deucher
Browse files

drm/amd/powerplay: raven 4k@60hz dp monitor always flicking 



[WHY] clock unit mis-match between caller DC and SMU interface.
      dc pass lock in mhz. the same unit as smu. no covert is needed.

[HOW] remove covert_10k_to_mhz in smu interface
      this fixes corruption issue with 4k @60 display and stutter
      mode enable

Reviewed-by: default avatarKenneth Feng <kenneth.feng@amd.com>
Signed-off-by: default avatarhersen wu <hersenxs.wu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 11f874c0

drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c

+6 −11
Original line number Diff line number Diff line
@@ -205,18 +205,13 @@ static int smu10_set_clock_limit(struct pp_hwmgr *hwmgr, const void *input) 
	return 0;

}



static inline uint32_t convert_10k_to_mhz(uint32_t clock)

{

	return (clock + 99) / 100;

}



static int smu10_set_min_deep_sleep_dcefclk(struct pp_hwmgr *hwmgr, uint32_t clock)

{

	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);



	if (smu10_data->need_min_deep_sleep_dcefclk &&

		smu10_data->deep_sleep_dcefclk != convert_10k_to_mhz(clock)) {

		smu10_data->deep_sleep_dcefclk = convert_10k_to_mhz(clock);

		smu10_data->deep_sleep_dcefclk != clock) {

		smu10_data->deep_sleep_dcefclk = clock;

		smum_send_msg_to_smc_with_parameter(hwmgr,

					PPSMC_MSG_SetMinDeepSleepDcefclk,

					smu10_data->deep_sleep_dcefclk);
@@ -229,8 +224,8 @@ static int smu10_set_hard_min_dcefclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t c 
	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);



	if (smu10_data->dcf_actual_hard_min_freq &&

		smu10_data->dcf_actual_hard_min_freq != convert_10k_to_mhz(clock)) {

		smu10_data->dcf_actual_hard_min_freq = convert_10k_to_mhz(clock);

		smu10_data->dcf_actual_hard_min_freq != clock) {

		smu10_data->dcf_actual_hard_min_freq = clock;

		smum_send_msg_to_smc_with_parameter(hwmgr,

					PPSMC_MSG_SetHardMinDcefclkByFreq,

					smu10_data->dcf_actual_hard_min_freq);
@@ -243,8 +238,8 @@ static int smu10_set_hard_min_fclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t cloc 
	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);



	if (smu10_data->f_actual_hard_min_freq &&

		smu10_data->f_actual_hard_min_freq != convert_10k_to_mhz(clock)) {

		smu10_data->f_actual_hard_min_freq = convert_10k_to_mhz(clock);

		smu10_data->f_actual_hard_min_freq != clock) {

		smu10_data->f_actual_hard_min_freq = clock;

		smum_send_msg_to_smc_with_parameter(hwmgr,

					PPSMC_MSG_SetHardMinFclkByFreq,

					smu10_data->f_actual_hard_min_freq);

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