Commit a65217a4 authored by Will Deacon's avatar Will Deacon
Browse files

iommu/arm-smmu: fix calculation of TCR.T0SZ 



T0SZ controls the input address range for TTBR0, so use the input
address range rather than the output address range for the calculation.
For stage-2, this means using the output size of stage-1.

Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent 7171511e

drivers/iommu/arm-smmu.c

+3 −1
Original line number Original line Diff line number Diff line
@@ -800,6 +800,8 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain) 
			reg = TTBCR_TG0_64K;

			reg = TTBCR_TG0_64K;





		if (!stage1) {

		if (!stage1) {

			reg |= (64 - smmu->s1_output_size) << TTBCR_T0SZ_SHIFT;



			switch (smmu->s2_output_size) {

			switch (smmu->s2_output_size) {

			case 32:

			case 32:

				reg |= (TTBCR2_ADDR_32 << TTBCR_PASIZE_SHIFT);

				reg |= (TTBCR2_ADDR_32 << TTBCR_PASIZE_SHIFT);
@@ -821,7 +823,7 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain) 
				break;

				break;

			}

			}

		} else {

		} else {

			reg |= (64 - smmu->s1_output_size) << TTBCR_T0SZ_SHIFT;

			reg |= (64 - smmu->input_size) << TTBCR_T0SZ_SHIFT;

		}

		}

	} else {

	} else {

		reg = 0;

		reg = 0;

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