Commit a6475c13 authored by Michal Simek's avatar Michal Simek
Browse files

microblaze: Enable PCI, missing files 



There are two parts of changes. The first is just enable
PCI in Makefiles and in Kconfig. The second is the rest of
missing files. I didn't want to add it with previous patch
because that patch is too big.

Current Microblaze toolchain has problem with weak symbols
that's why is necessary to apply this changes to be possible
to compile pci support.
Xilinx knows about this problem.

Signed-off-by: default avatarMichal Simek <monstr@monstr.eu>
parent d3afa58c

arch/microblaze/Kconfig

+15 −0
Original line number Diff line number Diff line
@@ -256,6 +256,21 @@ source "fs/Kconfig.binfmt" 


endmenu



menu "Bus Options"



config PCI

	bool "PCI support"



config PCI_DOMAINS

	def_bool PCI



config PCI_SYSCALL

	def_bool PCI



source "drivers/pci/Kconfig"



endmenu



source "net/Kconfig"



source "drivers/Kconfig"

arch/microblaze/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -50,6 +50,7 @@ libs-y += $(LIBGCC) 
core-y += arch/microblaze/kernel/

core-y += arch/microblaze/mm/

core-y += arch/microblaze/platform/

core-$(CONFIG_PCI) += arch/microblaze/pci/



drivers-$(CONFIG_OPROFILE) += arch/microblaze/oprofile/

arch/microblaze/include/asm/io.h

+15 −1
Original line number Diff line number Diff line
@@ -17,7 +17,21 @@ 
#include <linux/mm.h>          /* Get struct page {...} */

#include <asm-generic/iomap.h>



#ifndef CONFIG_PCI

#define _IO_BASE	0

#define _ISA_MEM_BASE	0

#define PCI_DRAM_OFFSET	0

#else

#define _IO_BASE	isa_io_base

#define _ISA_MEM_BASE	isa_mem_base

#define PCI_DRAM_OFFSET	pci_dram_offset

#endif



extern unsigned long isa_io_base;

extern unsigned long pci_io_base;

extern unsigned long pci_dram_offset;



extern resource_size_t isa_mem_base;



#define IO_SPACE_LIMIT (0xFFFFFFFF)

arch/microblaze/include/asm/pgtable.h

+15 −0
Original line number Diff line number Diff line
@@ -89,6 +89,21 @@ static inline pte_t pte_mkspecial(pte_t pte) { return pte; } 


#endif /* __ASSEMBLY__ */



/*

 * Macro to mark a page protection value as "uncacheable".

 */



#define _PAGE_CACHE_CTL	(_PAGE_GUARDED | _PAGE_NO_CACHE | \

							_PAGE_WRITETHRU)



#define pgprot_noncached(prot) \

			(__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \

					_PAGE_NO_CACHE | _PAGE_GUARDED))



#define pgprot_noncached_wc(prot) \

			 (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \

							_PAGE_NO_CACHE))



/*

 * The MicroBlaze MMU is identical to the PPC-40x MMU, and uses a hash

 * table containing PTEs, together with a set of 16 segment registers, to

arch/microblaze/include/asm/prom.h

+15 −0
Original line number Diff line number Diff line
@@ -31,6 +31,21 @@ 
/* Other Prototypes */

extern int early_uartlite_console(void);



#ifdef CONFIG_PCI

/*

 * PCI <-> OF matching functions

 * (XXX should these be here?)

 */

struct pci_bus;

struct pci_dev;

extern int pci_device_from_OF_node(struct device_node *node,

					u8 *bus, u8 *devfn);

extern struct device_node *pci_busdev_to_OF_node(struct pci_bus *bus,

							int devfn);

extern struct device_node *pci_device_to_OF_node(struct pci_dev *dev);

extern void pci_create_OF_bus_map(void);

#endif



/*

 * OF address retreival & translation

 */

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