Commit a636a982 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-next-3.8' of git://people.freedesktop.org/~agd5f/linux into drm-next 

Alex writes:
"adds support for the
asynchronous DMA engines on r6xx-SI.  These engines are used
for ttm bo moves and VM page table updates currently.  They
could also be exposed via the CS ioctl for userspace use,
but I haven't had a chance to add proper CS checker patches
for them yet.  These patches have been tested extensively
internally for months, so they should be pretty solid."

* 'drm-next-3.8' of git://people.freedesktop.org/~agd5f/linux:
  drm/radeon: use DMA engine for VM page table updates on SI
  drm/radeon: add dma engine support for vm pt updates on si (v2)
  drm/radeon: use DMA engine for VM page table updates on cayman/TN
  drm/radeon: add dma engine support for vm pt updates on ni (v5)
  drm/radeon: use async dma for ttm buffer moves on 6xx-SI
  drm/radeon/kms: add support for dma rings to radeon_test_moves()
  drm/radeon/kms: Add initial support for async DMA on SI
  drm/radeon/kms: Add initial support for async DMA on cayman/TN
  drm/radeon/kms: Add initial support for async DMA on evergreen
  drm/radeon/kms: Add initial support for async DMA on r6xx/r7xx
parents 97a875cb bf66a786

drivers/gpu/drm/radeon/evergreen.c

+197 −3
Original line number Diff line number Diff line
@@ -2034,6 +2034,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev) 
	WREG32(GB_ADDR_CONFIG, gb_addr_config);

	WREG32(DMIF_ADDR_CONFIG, gb_addr_config);

	WREG32(HDP_ADDR_CONFIG, gb_addr_config);

	WREG32(DMA_TILING_CONFIG, gb_addr_config);



	tmp = gb_addr_config & NUM_PIPES_MASK;

	tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.evergreen.max_backends,
@@ -2403,8 +2404,12 @@ void evergreen_disable_interrupt_state(struct radeon_device *rdev) 
					 CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);

		cayman_cp_int_cntl_setup(rdev, 1, 0);

		cayman_cp_int_cntl_setup(rdev, 2, 0);

		tmp = RREG32(CAYMAN_DMA1_CNTL) & ~TRAP_ENABLE;

		WREG32(CAYMAN_DMA1_CNTL, tmp);

	} else

		WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);

	tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;

	WREG32(DMA_CNTL, tmp);

	WREG32(GRBM_INT_CNTL, 0);

	WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);

	WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
@@ -2457,6 +2462,7 @@ int evergreen_irq_set(struct radeon_device *rdev) 
	u32 grbm_int_cntl = 0;

	u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;

	u32 afmt1 = 0, afmt2 = 0, afmt3 = 0, afmt4 = 0, afmt5 = 0, afmt6 = 0;

	u32 dma_cntl, dma_cntl1 = 0;



	if (!rdev->irq.installed) {

		WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
@@ -2484,6 +2490,8 @@ int evergreen_irq_set(struct radeon_device *rdev) 
	afmt5 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;

	afmt6 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;



	dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE;



	if (rdev->family >= CHIP_CAYMAN) {

		/* enable CP interrupts on all rings */

		if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
@@ -2506,6 +2514,19 @@ int evergreen_irq_set(struct radeon_device *rdev) 
		}

	}



	if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {

		DRM_DEBUG("r600_irq_set: sw int dma\n");

		dma_cntl |= TRAP_ENABLE;

	}



	if (rdev->family >= CHIP_CAYMAN) {

		dma_cntl1 = RREG32(CAYMAN_DMA1_CNTL) & ~TRAP_ENABLE;

		if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_DMA1_INDEX])) {

			DRM_DEBUG("r600_irq_set: sw int dma1\n");

			dma_cntl1 |= TRAP_ENABLE;

		}

	}



	if (rdev->irq.crtc_vblank_int[0] ||

	    atomic_read(&rdev->irq.pflip[0])) {

		DRM_DEBUG("evergreen_irq_set: vblank 0\n");
@@ -2591,6 +2612,12 @@ int evergreen_irq_set(struct radeon_device *rdev) 
		cayman_cp_int_cntl_setup(rdev, 2, cp_int_cntl2);

	} else

		WREG32(CP_INT_CNTL, cp_int_cntl);



	WREG32(DMA_CNTL, dma_cntl);



	if (rdev->family >= CHIP_CAYMAN)

		WREG32(CAYMAN_DMA1_CNTL, dma_cntl1);



	WREG32(GRBM_INT_CNTL, grbm_int_cntl);



	WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
@@ -3126,9 +3153,19 @@ restart_ih: 
			} else

				radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);

			break;

		case 224: /* DMA trap event */

			DRM_DEBUG("IH: DMA trap\n");

			radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);

			break;

		case 233: /* GUI IDLE */

			DRM_DEBUG("IH: GUI idle\n");

			break;

		case 244: /* DMA trap event */

			if (rdev->family >= CHIP_CAYMAN) {

				DRM_DEBUG("IH: DMA1 trap\n");

				radeon_fence_process(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);

			}

			break;

		default:

			DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);

			break;
@@ -3154,6 +3191,143 @@ restart_ih: 
	return IRQ_HANDLED;

}



/**

 * evergreen_dma_fence_ring_emit - emit a fence on the DMA ring

 *

 * @rdev: radeon_device pointer

 * @fence: radeon fence object

 *

 * Add a DMA fence packet to the ring to write

 * the fence seq number and DMA trap packet to generate

 * an interrupt if needed (evergreen-SI).

 */

void evergreen_dma_fence_ring_emit(struct radeon_device *rdev,

				   struct radeon_fence *fence)

{

	struct radeon_ring *ring = &rdev->ring[fence->ring];

	u64 addr = rdev->fence_drv[fence->ring].gpu_addr;

	/* write the fence */

	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0));

	radeon_ring_write(ring, addr & 0xfffffffc);

	radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));

	radeon_ring_write(ring, fence->seq);

	/* generate an interrupt */

	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0));

	/* flush HDP */

	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));

	radeon_ring_write(ring, (0xf << 16) | HDP_MEM_COHERENCY_FLUSH_CNTL);

	radeon_ring_write(ring, 1);

}



/**

 * evergreen_dma_ring_ib_execute - schedule an IB on the DMA engine

 *

 * @rdev: radeon_device pointer

 * @ib: IB object to schedule

 *

 * Schedule an IB in the DMA ring (evergreen).

 */

void evergreen_dma_ring_ib_execute(struct radeon_device *rdev,

				   struct radeon_ib *ib)

{

	struct radeon_ring *ring = &rdev->ring[ib->ring];



	if (rdev->wb.enabled) {

		u32 next_rptr = ring->wptr + 4;

		while ((next_rptr & 7) != 5)

			next_rptr++;

		next_rptr += 3;

		radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));

		radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);

		radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);

		radeon_ring_write(ring, next_rptr);

	}



	/* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.

	 * Pad as necessary with NOPs.

	 */

	while ((ring->wptr & 7) != 5)

		radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));

	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0, 0));

	radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));

	radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));



}



/**

 * evergreen_copy_dma - copy pages using the DMA engine

 *

 * @rdev: radeon_device pointer

 * @src_offset: src GPU address

 * @dst_offset: dst GPU address

 * @num_gpu_pages: number of GPU pages to xfer

 * @fence: radeon fence object

 *

 * Copy GPU paging using the DMA engine (evergreen-cayman).

 * Used by the radeon ttm implementation to move pages if

 * registered as the asic copy callback.

 */

int evergreen_copy_dma(struct radeon_device *rdev,

		       uint64_t src_offset, uint64_t dst_offset,

		       unsigned num_gpu_pages,

		       struct radeon_fence **fence)

{

	struct radeon_semaphore *sem = NULL;

	int ring_index = rdev->asic->copy.dma_ring_index;

	struct radeon_ring *ring = &rdev->ring[ring_index];

	u32 size_in_dw, cur_size_in_dw;

	int i, num_loops;

	int r = 0;



	r = radeon_semaphore_create(rdev, &sem);

	if (r) {

		DRM_ERROR("radeon: moving bo (%d).\n", r);

		return r;

	}



	size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4;

	num_loops = DIV_ROUND_UP(size_in_dw, 0xfffff);

	r = radeon_ring_lock(rdev, ring, num_loops * 5 + 11);

	if (r) {

		DRM_ERROR("radeon: moving bo (%d).\n", r);

		radeon_semaphore_free(rdev, &sem, NULL);

		return r;

	}



	if (radeon_fence_need_sync(*fence, ring->idx)) {

		radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,

					    ring->idx);

		radeon_fence_note_sync(*fence, ring->idx);

	} else {

		radeon_semaphore_free(rdev, &sem, NULL);

	}



	for (i = 0; i < num_loops; i++) {

		cur_size_in_dw = size_in_dw;

		if (cur_size_in_dw > 0xFFFFF)

			cur_size_in_dw = 0xFFFFF;

		size_in_dw -= cur_size_in_dw;

		radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw));

		radeon_ring_write(ring, dst_offset & 0xfffffffc);

		radeon_ring_write(ring, src_offset & 0xfffffffc);

		radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);

		radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);

		src_offset += cur_size_in_dw * 4;

		dst_offset += cur_size_in_dw * 4;

	}



	r = radeon_fence_emit(rdev, fence, ring->idx);

	if (r) {

		radeon_ring_unlock_undo(rdev, ring);

		return r;

	}



	radeon_ring_unlock_commit(rdev, ring);

	radeon_semaphore_free(rdev, &sem, *fence);



	return r;

}



static int evergreen_startup(struct radeon_device *rdev)

{

	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
@@ -3217,6 +3391,12 @@ static int evergreen_startup(struct radeon_device *rdev) 
		return r;

	}



	r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);

	if (r) {

		dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);

		return r;

	}



	/* Enable IRQ */

	r = r600_irq_init(rdev);

	if (r) {
@@ -3231,10 +3411,21 @@ static int evergreen_startup(struct radeon_device *rdev) 
			     0, 0xfffff, RADEON_CP_PACKET2);

	if (r)

		return r;



	ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];

	r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,

			     DMA_RB_RPTR, DMA_RB_WPTR,

			     2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));

	if (r)

		return r;



	r = evergreen_cp_load_microcode(rdev);

	if (r)

		return r;

	r = evergreen_cp_resume(rdev);

	if (r)

		return r;

	r = r600_dma_resume(rdev);

	if (r)

		return r;
@@ -3283,11 +3474,9 @@ int evergreen_resume(struct radeon_device *rdev) 


int evergreen_suspend(struct radeon_device *rdev)

{

	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];



	r600_audio_fini(rdev);

	r700_cp_stop(rdev);

	ring->ready = false;

	r600_dma_stop(rdev);

	evergreen_irq_suspend(rdev);

	radeon_wb_disable(rdev);

	evergreen_pcie_gart_disable(rdev);
@@ -3364,6 +3553,9 @@ int evergreen_init(struct radeon_device *rdev) 
	rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;

	r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);



	rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;

	r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);



	rdev->ih.ring_obj = NULL;

	r600_ih_ring_init(rdev, 64 * 1024);
@@ -3376,6 +3568,7 @@ int evergreen_init(struct radeon_device *rdev) 
	if (r) {

		dev_err(rdev->dev, "disabling GPU acceleration\n");

		r700_cp_fini(rdev);

		r600_dma_fini(rdev);

		r600_irq_fini(rdev);

		radeon_wb_fini(rdev);

		radeon_ib_pool_fini(rdev);
@@ -3403,6 +3596,7 @@ void evergreen_fini(struct radeon_device *rdev) 
	r600_audio_fini(rdev);

	r600_blit_fini(rdev);

	r700_cp_fini(rdev);

	r600_dma_fini(rdev);

	r600_irq_fini(rdev);

	radeon_wb_fini(rdev);

	radeon_ib_pool_fini(rdev);

drivers/gpu/drm/radeon/evergreend.h

+31 −0
Original line number Diff line number Diff line
@@ -905,6 +905,37 @@ 
#       define DC_HPDx_RX_INT_TIMER(x)                    ((x) << 16)

#       define DC_HPDx_EN                                 (1 << 28)



/* ASYNC DMA */

#define DMA_RB_RPTR                                       0xd008

#define DMA_RB_WPTR                                       0xd00c



#define DMA_CNTL                                          0xd02c

#       define TRAP_ENABLE                                (1 << 0)

#       define SEM_INCOMPLETE_INT_ENABLE                  (1 << 1)

#       define SEM_WAIT_INT_ENABLE                        (1 << 2)

#       define DATA_SWAP_ENABLE                           (1 << 3)

#       define FENCE_SWAP_ENABLE                          (1 << 4)

#       define CTXEMPTY_INT_ENABLE                        (1 << 28)

#define DMA_TILING_CONFIG  				  0xD0B8



#define CAYMAN_DMA1_CNTL                                  0xd82c



/* async DMA packets */

#define DMA_PACKET(cmd, t, s, n)	((((cmd) & 0xF) << 28) |	\

					 (((t) & 0x1) << 23) |		\

					 (((s) & 0x1) << 22) |		\

					 (((n) & 0xFFFFF) << 0))

/* async DMA Packet types */

#define	DMA_PACKET_WRITE				  0x2

#define	DMA_PACKET_COPY					  0x3

#define	DMA_PACKET_INDIRECT_BUFFER			  0x4

#define	DMA_PACKET_SEMAPHORE				  0x5

#define	DMA_PACKET_FENCE				  0x6

#define	DMA_PACKET_TRAP					  0x7

#define	DMA_PACKET_SRBM_WRITE				  0x9

#define	DMA_PACKET_CONSTANT_FILL			  0xd

#define	DMA_PACKET_NOP					  0xf



/* PCIE link stuff */

#define PCIE_LC_TRAINING_CNTL                             0xa1 /* PCIE_P */

#define PCIE_LC_LINK_WIDTH_CNTL                           0xa2 /* PCIE_P */

drivers/gpu/drm/radeon/ni.c

+319 −22
Original line number Diff line number Diff line
@@ -611,6 +611,8 @@ static void cayman_gpu_init(struct radeon_device *rdev) 
	WREG32(GB_ADDR_CONFIG, gb_addr_config);

	WREG32(DMIF_ADDR_CONFIG, gb_addr_config);

	WREG32(HDP_ADDR_CONFIG, gb_addr_config);

	WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);

	WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);



	tmp = gb_addr_config & NUM_PIPES_MASK;

	tmp = r6xx_remap_render_backend(rdev, tmp,
@@ -915,6 +917,7 @@ static void cayman_cp_enable(struct radeon_device *rdev, bool enable) 
		radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);

		WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));

		WREG32(SCRATCH_UMSK, 0);

		rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;

	}

}
@@ -1128,6 +1131,181 @@ static int cayman_cp_resume(struct radeon_device *rdev) 
	return 0;

}



/*

 * DMA

 * Starting with R600, the GPU has an asynchronous

 * DMA engine.  The programming model is very similar

 * to the 3D engine (ring buffer, IBs, etc.), but the

 * DMA controller has it's own packet format that is

 * different form the PM4 format used by the 3D engine.

 * It supports copying data, writing embedded data,

 * solid fills, and a number of other things.  It also

 * has support for tiling/detiling of buffers.

 * Cayman and newer support two asynchronous DMA engines.

 */

/**

 * cayman_dma_ring_ib_execute - Schedule an IB on the DMA engine

 *

 * @rdev: radeon_device pointer

 * @ib: IB object to schedule

 *

 * Schedule an IB in the DMA ring (cayman-SI).

 */

void cayman_dma_ring_ib_execute(struct radeon_device *rdev,

				struct radeon_ib *ib)

{

	struct radeon_ring *ring = &rdev->ring[ib->ring];



	if (rdev->wb.enabled) {

		u32 next_rptr = ring->wptr + 4;

		while ((next_rptr & 7) != 5)

			next_rptr++;

		next_rptr += 3;

		radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));

		radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);

		radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);

		radeon_ring_write(ring, next_rptr);

	}



	/* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.

	 * Pad as necessary with NOPs.

	 */

	while ((ring->wptr & 7) != 5)

		radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));

	radeon_ring_write(ring, DMA_IB_PACKET(DMA_PACKET_INDIRECT_BUFFER, ib->vm ? ib->vm->id : 0, 0));

	radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));

	radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));



}



/**

 * cayman_dma_stop - stop the async dma engines

 *

 * @rdev: radeon_device pointer

 *

 * Stop the async dma engines (cayman-SI).

 */

void cayman_dma_stop(struct radeon_device *rdev)

{

	u32 rb_cntl;



	radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);



	/* dma0 */

	rb_cntl = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);

	rb_cntl &= ~DMA_RB_ENABLE;

	WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, rb_cntl);



	/* dma1 */

	rb_cntl = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);

	rb_cntl &= ~DMA_RB_ENABLE;

	WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, rb_cntl);



	rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false;

	rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready = false;

}



/**

 * cayman_dma_resume - setup and start the async dma engines

 *

 * @rdev: radeon_device pointer

 *

 * Set up the DMA ring buffers and enable them. (cayman-SI).

 * Returns 0 for success, error for failure.

 */

int cayman_dma_resume(struct radeon_device *rdev)

{

	struct radeon_ring *ring;

	u32 rb_cntl, dma_cntl;

	u32 rb_bufsz;

	u32 reg_offset, wb_offset;

	int i, r;



	/* Reset dma */

	WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA | SOFT_RESET_DMA1);

	RREG32(SRBM_SOFT_RESET);

	udelay(50);

	WREG32(SRBM_SOFT_RESET, 0);



	for (i = 0; i < 2; i++) {

		if (i == 0) {

			ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];

			reg_offset = DMA0_REGISTER_OFFSET;

			wb_offset = R600_WB_DMA_RPTR_OFFSET;

		} else {

			ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];

			reg_offset = DMA1_REGISTER_OFFSET;

			wb_offset = CAYMAN_WB_DMA1_RPTR_OFFSET;

		}



		WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0);

		WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0);



		/* Set ring buffer size in dwords */

		rb_bufsz = drm_order(ring->ring_size / 4);

		rb_cntl = rb_bufsz << 1;

#ifdef __BIG_ENDIAN

		rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE;

#endif

		WREG32(DMA_RB_CNTL + reg_offset, rb_cntl);



		/* Initialize the ring buffer's read and write pointers */

		WREG32(DMA_RB_RPTR + reg_offset, 0);

		WREG32(DMA_RB_WPTR + reg_offset, 0);



		/* set the wb address whether it's enabled or not */

		WREG32(DMA_RB_RPTR_ADDR_HI + reg_offset,

		       upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFF);

		WREG32(DMA_RB_RPTR_ADDR_LO + reg_offset,

		       ((rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC));



		if (rdev->wb.enabled)

			rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE;



		WREG32(DMA_RB_BASE + reg_offset, ring->gpu_addr >> 8);



		/* enable DMA IBs */

		WREG32(DMA_IB_CNTL + reg_offset, DMA_IB_ENABLE | CMD_VMID_FORCE);



		dma_cntl = RREG32(DMA_CNTL + reg_offset);

		dma_cntl &= ~CTXEMPTY_INT_ENABLE;

		WREG32(DMA_CNTL + reg_offset, dma_cntl);



		ring->wptr = 0;

		WREG32(DMA_RB_WPTR + reg_offset, ring->wptr << 2);



		ring->rptr = RREG32(DMA_RB_RPTR + reg_offset) >> 2;



		WREG32(DMA_RB_CNTL + reg_offset, rb_cntl | DMA_RB_ENABLE);



		ring->ready = true;



		r = radeon_ring_test(rdev, ring->idx, ring);

		if (r) {

			ring->ready = false;

			return r;

		}

	}



	radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);



	return 0;

}



/**

 * cayman_dma_fini - tear down the async dma engines

 *

 * @rdev: radeon_device pointer

 *

 * Stop the async dma engines and free the rings (cayman-SI).

 */

void cayman_dma_fini(struct radeon_device *rdev)

{

	cayman_dma_stop(rdev);

	radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]);

	radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]);

}



static int cayman_gpu_soft_reset(struct radeon_device *rdev)

{

	struct evergreen_mc_save save;
@@ -1218,6 +1396,32 @@ int cayman_asic_reset(struct radeon_device *rdev) 
	return cayman_gpu_soft_reset(rdev);

}



/**

 * cayman_dma_is_lockup - Check if the DMA engine is locked up

 *

 * @rdev: radeon_device pointer

 * @ring: radeon_ring structure holding ring information

 *

 * Check if the async DMA engine is locked up (cayman-SI).

 * Returns true if the engine appears to be locked up, false if not.

 */

bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)

{

	u32 dma_status_reg;



	if (ring->idx == R600_RING_TYPE_DMA_INDEX)

		dma_status_reg = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);

	else

		dma_status_reg = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);

	if (dma_status_reg & DMA_IDLE) {

		radeon_ring_lockup_update(ring);

		return false;

	}

	/* force ring activities */

	radeon_ring_force_activity(rdev, ring);

	return radeon_ring_test_lockup(rdev, ring);

}



static int cayman_startup(struct radeon_device *rdev)

{

	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
@@ -1299,6 +1503,18 @@ static int cayman_startup(struct radeon_device *rdev) 
		return r;

	}



	r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);

	if (r) {

		dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);

		return r;

	}



	r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);

	if (r) {

		dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);

		return r;

	}



	/* Enable IRQ */

	r = r600_irq_init(rdev);

	if (r) {
@@ -1313,6 +1529,23 @@ static int cayman_startup(struct radeon_device *rdev) 
			     0, 0xfffff, RADEON_CP_PACKET2);

	if (r)

		return r;



	ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];

	r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,

			     DMA_RB_RPTR + DMA0_REGISTER_OFFSET,

			     DMA_RB_WPTR + DMA0_REGISTER_OFFSET,

			     2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));

	if (r)

		return r;



	ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];

	r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,

			     DMA_RB_RPTR + DMA1_REGISTER_OFFSET,

			     DMA_RB_WPTR + DMA1_REGISTER_OFFSET,

			     2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));

	if (r)

		return r;



	r = cayman_cp_load_microcode(rdev);

	if (r)

		return r;
@@ -1320,6 +1553,10 @@ static int cayman_startup(struct radeon_device *rdev) 
	if (r)

		return r;



	r = cayman_dma_resume(rdev);

	if (r)

		return r;



	r = radeon_ib_pool_init(rdev);

	if (r) {

		dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
@@ -1364,7 +1601,7 @@ int cayman_suspend(struct radeon_device *rdev) 
{

	r600_audio_fini(rdev);

	cayman_cp_enable(rdev, false);

	rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;

	cayman_dma_stop(rdev);

	evergreen_irq_suspend(rdev);

	radeon_wb_disable(rdev);

	cayman_pcie_gart_disable(rdev);
@@ -1431,6 +1668,14 @@ int cayman_init(struct radeon_device *rdev) 
	ring->ring_obj = NULL;

	r600_ring_init(rdev, ring, 1024 * 1024);



	ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];

	ring->ring_obj = NULL;

	r600_ring_init(rdev, ring, 64 * 1024);



	ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];

	ring->ring_obj = NULL;

	r600_ring_init(rdev, ring, 64 * 1024);



	rdev->ih.ring_obj = NULL;

	r600_ih_ring_init(rdev, 64 * 1024);
@@ -1443,6 +1688,7 @@ int cayman_init(struct radeon_device *rdev) 
	if (r) {

		dev_err(rdev->dev, "disabling GPU acceleration\n");

		cayman_cp_fini(rdev);

		cayman_dma_fini(rdev);

		r600_irq_fini(rdev);

		if (rdev->flags & RADEON_IS_IGP)

			si_rlc_fini(rdev);
@@ -1473,6 +1719,7 @@ void cayman_fini(struct radeon_device *rdev) 
{

	r600_blit_fini(rdev);

	cayman_cp_fini(rdev);

	cayman_dma_fini(rdev);

	r600_irq_fini(rdev);

	if (rdev->flags & RADEON_IS_IGP)

		si_rlc_fini(rdev);
@@ -1548,9 +1795,12 @@ void cayman_vm_set_page(struct radeon_device *rdev, uint64_t pe, 
{

	struct radeon_ring *ring = &rdev->ring[rdev->asic->vm.pt_ring_index];

	uint32_t r600_flags = cayman_vm_page_flags(rdev, flags);

	uint64_t value;

	unsigned ndw;



	if (rdev->asic->vm.pt_ring_index == RADEON_RING_TYPE_GFX_INDEX) {

		while (count) {

		unsigned ndw = 1 + count * 2;

			ndw = 1 + count * 2;

			if (ndw > 0x3FFF)

				ndw = 0x3FFF;
@@ -1558,23 +1808,47 @@ void cayman_vm_set_page(struct radeon_device *rdev, uint64_t pe, 
			radeon_ring_write(ring, pe);

			radeon_ring_write(ring, upper_32_bits(pe) & 0xff);

			for (; ndw > 1; ndw -= 2, --count, pe += 8) {

			uint64_t value = 0;

				if (flags & RADEON_VM_PAGE_SYSTEM) {

					value = radeon_vm_map_gart(rdev, addr);

					value &= 0xFFFFFFFFFFFFF000ULL;

				addr += incr;



				} else if (flags & RADEON_VM_PAGE_VALID) {

					value = addr;

				} else {

					value = 0;

				}

				addr += incr;

				value |= r600_flags;

				radeon_ring_write(ring, value);

				radeon_ring_write(ring, upper_32_bits(value));

			}

		}

	} else {

		while (count) {

			ndw = count * 2;

			if (ndw > 0xFFFFE)

				ndw = 0xFFFFE;



			/* for non-physically contiguous pages (system) */

			radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, ndw));

			radeon_ring_write(ring, pe);

			radeon_ring_write(ring, upper_32_bits(pe) & 0xff);

			for (; ndw > 0; ndw -= 2, --count, pe += 8) {

				if (flags & RADEON_VM_PAGE_SYSTEM) {

					value = radeon_vm_map_gart(rdev, addr);

					value &= 0xFFFFFFFFFFFFF000ULL;

				} else if (flags & RADEON_VM_PAGE_VALID) {

					value = addr;

				} else {

					value = 0;

				}

				addr += incr;

				value |= r600_flags;

				radeon_ring_write(ring, value);

				radeon_ring_write(ring, upper_32_bits(value));

			}

		}

	}

}



/**

 * cayman_vm_flush - vm flush using the CP
@@ -1606,3 +1880,26 @@ void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) 
	radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));

	radeon_ring_write(ring, 0x0);

}



void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)

{

	struct radeon_ring *ring = &rdev->ring[ridx];



	if (vm == NULL)

		return;



	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));

	radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2));

	radeon_ring_write(ring, vm->pd_gpu_addr >> 12);



	/* flush hdp cache */

	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));

	radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));

	radeon_ring_write(ring, 1);



	/* bits 0-7 are the VM contexts0-7 */

	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));

	radeon_ring_write(ring, (0xf << 16) | (VM_INVALIDATE_REQUEST >> 2));

	radeon_ring_write(ring, 1 << vm->id);

}

drivers/gpu/drm/radeon/nid.h

+75 −0

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/radeon/r600.c

+469 −2

File changed.

Preview size limit exceeded, changes collapsed.

CRA Git | Maintained and supported by SUSTech CRA and CCSE