Commit a618a734 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'reset-for-4.12-1' of git://git.pengutronix.de/git/pza/linux into next/drivers 

Reset controller changes for v4.12

- make reset drivers with bool Kconfig options explicitly non-modular
- fix uniphier non-static symbol warnings
- fix socfpga nr_resets property
- new drivers for the Arria10 and i.MX7 system reset controllers
- fix sunxi 64-bit compilation

* tag 'reset-for-4.12-1' of git://git.pengutronix.de/git/pza/linux

:
  reset: sunxi: fix for 64-bit compilation
  reset: Add Altera Arria10 SR Reset Controller
  dt-bindings: reset: a10sr: Add Arria10 SR Reset Controller offsets
  reset: Add i.MX7 SRC reset driver
  reset-socfpga: Fix nr_resets property
  reset: uniphier: fix non static symbol warnings
  reset: pistachio: make it explicitly non-modular
  reset: ath79: make it explicitly non-modular
  reset: oxnas: make it explicitly non-modular
  reset: meson: make it explicitly non-modular

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 4495c08e 11282a49

Documentation/devicetree/bindings/reset/fsl,imx7-src.txt

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Freescale i.MX7 System Reset Controller

======================================



Please also refer to reset.txt in this directory for common reset

controller binding usage.



Required properties:

- compatible: Should be "fsl,imx7-src", "syscon"

- reg: should be register base and length as documented in the

  datasheet

- interrupts: Should contain SRC interrupt

- #reset-cells: 1, see below



example:



src: reset-controller@30390000 {

     compatible = "fsl,imx7d-src", "syscon";

     reg = <0x30390000 0x2000>;

     interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;

     #reset-cells = <1>;

};





Specifying reset lines connected to IP modules

==============================================



The system reset controller can be used to reset various set of

peripherals. Device nodes that need access to reset lines should

specify them as a reset phandle in their corresponding node as

specified in reset.txt.



Example:



	pcie: pcie@33800000 {



		...



		resets = <&src IMX7_RESET_PCIEPHY>,

			 <&src IMX7_RESET_PCIE_CTRL_APPS_EN>;

		reset-names = "pciephy", "apps";



		...

        };





For list of all valid reset indicies see

<dt-bindings/reset/imx7-reset.h>

MAINTAINERS

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@@ -653,7 +653,9 @@ M: Thor Thayer <thor.thayer@linux.intel.com> 
S:	Maintained

F:	drivers/gpio/gpio-altera-a10sr.c

F:	drivers/mfd/altera-a10sr.c

F:	drivers/reset/reset-a10sr.c

F:	include/linux/mfd/altera-a10sr.h

F:	include/dt-bindings/reset/altr,rst-mgr-a10sr.h



ALTERA TRIPLE SPEED ETHERNET DRIVER

M:	Vince Bridgers <vbridger@opensource.altera.com>

drivers/reset/Kconfig

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@@ -14,6 +14,13 @@ menuconfig RESET_CONTROLLER 


if RESET_CONTROLLER



config RESET_A10SR

	tristate "Altera Arria10 System Resource Reset"

	depends on MFD_ALTERA_A10SR

	help

	  This option enables support for the external reset functions for

	  peripheral PHYs on the Altera Arria10 System Resource Chip.



config RESET_ATH79

	bool "AR71xx Reset Driver" if COMPILE_TEST

	default ATH79
@@ -27,6 +34,13 @@ config RESET_BERLIN 
	help

	  This enables the reset controller driver for Marvell Berlin SoCs.



config RESET_IMX7

	bool "i.MX7 Reset Driver" if COMPILE_TEST

	default SOC_IMX7D

	select MFD_SYSCON

	help

	  This enables the reset controller driver for i.MX7 SoCs.



config RESET_LPC18XX

	bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST

	default ARCH_LPC18XX

drivers/reset/Makefile

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@@ -2,8 +2,10 @@ obj-y += core.o 
obj-y += hisilicon/

obj-$(CONFIG_ARCH_STI) += sti/

obj-$(CONFIG_ARCH_TEGRA) += tegra/

obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o

obj-$(CONFIG_RESET_ATH79) += reset-ath79.o

obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o

obj-$(CONFIG_RESET_IMX7) += reset-imx7.o

obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o

obj-$(CONFIG_RESET_MESON) += reset-meson.o

obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
@@ -15,3 +17,4 @@ obj-$(CONFIG_TI_SYSCON_RESET) += reset-ti-syscon.o 
obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o

obj-$(CONFIG_RESET_ZX2967) += reset-zx2967.o

obj-$(CONFIG_RESET_ZYNQ) += reset-zynq.o

drivers/reset/reset-a10sr.c

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/*

 *  Copyright Intel Corporation (C) 2017. All Rights Reserved

 *

 * This program is free software; you can redistribute it and/or modify it

 * under the terms and conditions of the GNU General Public License,

 * version 2, as published by the Free Software Foundation.

 *

 * This program is distributed in the hope it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

 * more details.

 *

 * You should have received a copy of the GNU General Public License along with

 * this program.  If not, see <http://www.gnu.org/licenses/>.

 *

 * Reset driver for Altera Arria10 MAX5 System Resource Chip

 *

 * Adapted from reset-socfpga.c

 */



#include <linux/err.h>

#include <linux/mfd/altera-a10sr.h>

#include <linux/module.h>

#include <linux/of.h>

#include <linux/platform_device.h>

#include <linux/reset-controller.h>



#include <dt-bindings/reset/altr,rst-mgr-a10sr.h>



struct a10sr_reset {

	struct reset_controller_dev     rcdev;

	struct regmap *regmap;

};



static inline struct a10sr_reset *to_a10sr_rst(struct reset_controller_dev *rc)

{

	return container_of(rc, struct a10sr_reset, rcdev);

}



static inline int a10sr_reset_shift(unsigned long id)

{

	switch (id) {

	case A10SR_RESET_ENET_HPS:

		return 1;

	case A10SR_RESET_PCIE:

	case A10SR_RESET_FILE:

	case A10SR_RESET_BQSPI:

	case A10SR_RESET_USB:

		return id + 11;

	default:

		return -EINVAL;

	}

}



static int a10sr_reset_update(struct reset_controller_dev *rcdev,

			      unsigned long id, bool assert)

{

	struct a10sr_reset *a10r = to_a10sr_rst(rcdev);

	int offset = a10sr_reset_shift(id);

	u8 mask = ALTR_A10SR_REG_BIT_MASK(offset);

	int index = ALTR_A10SR_HPS_RST_REG + ALTR_A10SR_REG_OFFSET(offset);



	return regmap_update_bits(a10r->regmap, index, mask, assert ? 0 : mask);

}



static int a10sr_reset_assert(struct reset_controller_dev *rcdev,

			      unsigned long id)

{

	return a10sr_reset_update(rcdev, id, true);

}



static int a10sr_reset_deassert(struct reset_controller_dev *rcdev,

				unsigned long id)

{

	return a10sr_reset_update(rcdev, id, false);

}



static int a10sr_reset_status(struct reset_controller_dev *rcdev,

			      unsigned long id)

{

	int ret;

	struct a10sr_reset *a10r = to_a10sr_rst(rcdev);

	int offset = a10sr_reset_shift(id);

	u8 mask = ALTR_A10SR_REG_BIT_MASK(offset);

	int index = ALTR_A10SR_HPS_RST_REG + ALTR_A10SR_REG_OFFSET(offset);

	unsigned int value;



	ret = regmap_read(a10r->regmap, index, &value);

	if (ret < 0)

		return ret;



	return !!(value & mask);

}



static const struct reset_control_ops a10sr_reset_ops = {

	.assert		= a10sr_reset_assert,

	.deassert	= a10sr_reset_deassert,

	.status		= a10sr_reset_status,

};



static int a10sr_reset_probe(struct platform_device *pdev)

{

	struct altr_a10sr *a10sr = dev_get_drvdata(pdev->dev.parent);

	struct a10sr_reset *a10r;



	a10r = devm_kzalloc(&pdev->dev, sizeof(struct a10sr_reset),

			    GFP_KERNEL);

	if (!a10r)

		return -ENOMEM;



	a10r->rcdev.owner = THIS_MODULE;

	a10r->rcdev.nr_resets = A10SR_RESET_NUM;

	a10r->rcdev.ops = &a10sr_reset_ops;

	a10r->rcdev.of_node = pdev->dev.of_node;

	a10r->regmap = a10sr->regmap;



	platform_set_drvdata(pdev, a10r);



	return devm_reset_controller_register(&pdev->dev, &a10r->rcdev);

}



static const struct of_device_id a10sr_reset_of_match[] = {

	{ .compatible = "altr,a10sr-reset" },

	{ },

};

MODULE_DEVICE_TABLE(of, a10sr_reset_of_match);



static struct platform_driver a10sr_reset_driver = {

	.probe	= a10sr_reset_probe,

	.driver = {

		.name		= "altr_a10sr_reset",

	},

};

module_platform_driver(a10sr_reset_driver);



MODULE_AUTHOR("Thor Thayer <thor.thayer@linux.intel.com>");

MODULE_DESCRIPTION("Altera Arria10 System Resource Reset Controller Driver");

MODULE_LICENSE("GPL v2");

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