Commit a600622c authored by Manasi Navare's avatar Manasi Navare
Browse files

drm/i915/dp: Disable DSC in source by disabling DSS CTL bits 



1. Disable Left/right VDSC branch in DSS Ctrl reg
    depending on the number of VDSC engines being used
2. Disable joiner in DSS Ctrl reg

v4:
* Remove encoder, make crtc_state const (Ville)
v3 (From Manasi):
* Add Disable PG2 for VDSC on eDP
v2 (From Manasi):
* Use old_crtc_state to find dsc params
* Add a condition to disable only if
dsc state compression is enabled
* Use correct DSS CTL regs

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: default avatarManasi Navare <manasi.d.navare@intel.com>
Signed-off-by: default avatarGaurav K Singh <gaurav.k.singh@intel.com>
Reviewed-by: default avatarAnusha Srivatsa <anusha.srivatsa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181128202628.20238-12-manasi.d.navare@intel.com
parent a311b0b5

drivers/gpu/drm/i915/i915_drv.h

+1 −0
Original line number Diff line number Diff line
@@ -3342,6 +3342,7 @@ extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, 
				  bool enable);

void intel_dsc_enable(struct intel_encoder *encoder,

		      const struct intel_crtc_state *crtc_state);

void intel_dsc_disable(const struct intel_crtc_state *crtc_state);



int i915_reg_read_ioctl(struct drm_device *dev, void *data,

			struct drm_file *file);

drivers/gpu/drm/i915/intel_display.c

+2 −0
Original line number Diff line number Diff line
@@ -5923,6 +5923,8 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state, 
	if (!transcoder_is_dsi(cpu_transcoder))

		intel_ddi_disable_transcoder_func(old_crtc_state);



	intel_dsc_disable(old_crtc_state);



	if (INTEL_GEN(dev_priv) >= 9)

		skylake_scaler_disable(intel_crtc);

	else

drivers/gpu/drm/i915/intel_vdsc.c

+31 −0
Original line number Diff line number Diff line
@@ -1029,3 +1029,34 @@ void intel_dsc_enable(struct intel_encoder *encoder, 
	I915_WRITE(dss_ctl1_reg, dss_ctl1_val);

	I915_WRITE(dss_ctl2_reg, dss_ctl2_val);

}



void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)

{

	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	enum pipe pipe = crtc->pipe;

	i915_reg_t dss_ctl1_reg, dss_ctl2_reg;

	u32 dss_ctl1_val = 0, dss_ctl2_val = 0;



	if (!old_crtc_state->dsc_params.compression_enable)

		return;



	if (old_crtc_state->cpu_transcoder == TRANSCODER_EDP) {

		dss_ctl1_reg = DSS_CTL1;

		dss_ctl2_reg = DSS_CTL2;

	} else {

		dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe);

		dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);

	}

	dss_ctl1_val = I915_READ(dss_ctl1_reg);

	if (dss_ctl1_val & JOINER_ENABLE)

		dss_ctl1_val &= ~JOINER_ENABLE;

	I915_WRITE(dss_ctl1_reg, dss_ctl1_val);



	dss_ctl2_val = I915_READ(dss_ctl2_reg);

	if (dss_ctl2_val & LEFT_BRANCH_VDSC_ENABLE ||

	    dss_ctl2_val & RIGHT_BRANCH_VDSC_ENABLE)

		dss_ctl2_val &= ~(LEFT_BRANCH_VDSC_ENABLE |

				  RIGHT_BRANCH_VDSC_ENABLE);

	I915_WRITE(dss_ctl2_reg, dss_ctl2_val);

}

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