Merge https://gitlab.freedesktop.org/drm/msm into drm-next (a5f2fafe) · Commits · 戴 / test

Documentation/devicetree/bindings/display/msm/gmu.txt

0 → 100644

+59 −0

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		Qualcomm adreno/snapdragon GMU (Graphics management unit)

		The GMU is a programmable power controller for the GPU. the CPU controls the
		GMU which in turn handles power controls for the GPU.

		Required properties:
		- compatible: "qcom,adreno-gmu-XYZ.W", "qcom,adreno-gmu"
		for example: "qcom,adreno-gmu-630.2", "qcom,adreno-gmu"
		Note that you need to list the less specific "qcom,adreno-gmu"
		for generic matches and the more specific identifier to identify
		the specific device.
		- reg: Physical base address and length of the GMU registers.
		- reg-names: Matching names for the register regions
		* "gmu"
		* "gmu_pdc"
		* "gmu_pdc_seg"
		- interrupts: The interrupt signals from the GMU.
		- interrupt-names: Matching names for the interrupts
		* "hfi"
		* "gmu"
		- clocks: phandles to the device clocks
		- clock-names: Matching names for the clocks
		* "gmu"
		* "cxo"
		* "axi"
		* "mnoc"
		- power-domains: should be <&clock_gpucc GPU_CX_GDSC>
		- iommus: phandle to the adreno iommu
		- operating-points-v2: phandle to the OPP operating points

		Example:

		/ {
		...

		gmu: gmu@506a000 {
		compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";

		reg = <0x506a000 0x30000>,
		<0xb280000 0x10000>,
		<0xb480000 0x10000>;
		reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";

		interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
		<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "hfi", "gmu";

		clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
		<&gpucc GPU_CC_CXO_CLK>,
		<&gcc GCC_DDRSS_GPU_AXI_CLK>,
		<&gcc GCC_GPU_MEMNOC_GFX_CLK>;
		clock-names = "gmu", "cxo", "axi", "memnoc";

		power-domains = <&gpucc GPU_CX_GDSC>;
		iommus = <&adreno_smmu 5>;

		operating-points-v2 = <&gmu_opp_table>;
		};
		};

Documentation/devicetree/bindings/display/msm/gpu.txt

+39 −3

Original line number	Diff line number	Diff line
		@@ -10,14 +10,23 @@ Required properties:
		If "amd,imageon" is used, there should be no top level msm device.
		- reg: Physical base address and length of the controller's registers.
		- interrupts: The interrupt signal from the gpu.
		- clocks: device clocks
		- clocks: device clocks (if applicable)
		See ../clocks/clock-bindings.txt for details.
		- clock-names: the following clocks are required:
		- clock-names: the following clocks are required by a3xx, a4xx and a5xx
		cores:
		* "core"
		* "iface"
		* "mem_iface"
		For GMU attached devices the GPU clocks are not used and are not required. The
		following devices should not list clocks:
		- qcom,adreno-630.2
		- iommus: optional phandle to an adreno iommu instance
		- operating-points-v2: optional phandle to the OPP operating points
		- qcom,gmu: For GMU attached devices a phandle to the GMU device that will
		control the power for the GPU. Applicable targets:
		- qcom,adreno-630.2

		Example:
		Example 3xx/4xx/a5xx:

		/ {
		...
		@@ -37,3 +46,30 @@ Example:
		<&mmcc MMSS_IMEM_AHB_CLK>;
		};
		};

		Example a6xx (with GMU):

		/ {
		...

		gpu@5000000 {
		compatible = "qcom,adreno-630.2", "qcom,adreno";
		#stream-id-cells = <16>;

		reg = <0x5000000 0x40000>, <0x509e000 0x10>;
		reg-names = "kgsl_3d0_reg_memory", "cx_mem";

		/*
		* Look ma, no clocks! The GPU clocks and power are
		* controlled entirely by the GMU
		*/

		interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;

		iommus = <&adreno_smmu 0>;

		operating-points-v2 = <&gpu_opp_table>;

		qcom,gmu = <&gmu>;
		};
		};

MAINTAINERS

+2 −1

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		@@ -4851,10 +4851,11 @@ F: Documentation/devicetree/bindings/display/multi-inno,mi0283qt.txt

		DRM DRIVER FOR MSM ADRENO GPU
		M: Rob Clark <robdclark@gmail.com>
		M: Sean Paul <sean@poorly.run>
		L: linux-arm-msm@vger.kernel.org
		L: dri-devel@lists.freedesktop.org
		L: freedreno@lists.freedesktop.org
		T: git git://people.freedesktop.org/~robclark/linux
		T: git https://gitlab.freedesktop.org/drm/msm.git
		S: Maintained
		F: drivers/gpu/drm/msm/
		F: include/uapi/drm/msm_drm.h

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

+2 −7

Original line number	Diff line number	Diff line
		@@ -465,8 +465,6 @@ static void _dpu_crtc_setup_mixer_for_encoder(
		return;
		}

		mixer->encoder = enc;

		cstate->num_mixers++;
		DPU_DEBUG("setup mixer %d: lm %d\n",
		i, mixer->hw_lm->idx - LM_0);
		@@ -718,11 +716,8 @@ void dpu_crtc_commit_kickoff(struct drm_crtc *crtc, bool async)
		* may delay and flush at an irq event (e.g. ppdone)
		*/
		drm_for_each_encoder_mask(encoder, crtc->dev,
		crtc->state->encoder_mask) {
		struct dpu_encoder_kickoff_params params = { 0 };
		dpu_encoder_prepare_for_kickoff(encoder, &params, async);
		}

		crtc->state->encoder_mask)
		dpu_encoder_prepare_for_kickoff(encoder, async);

		if (!async) {
		/* wait for frame_event_done completion */

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h

+0 −2

Original line number	Diff line number	Diff line
		@@ -84,14 +84,12 @@ struct dpu_crtc_smmu_state_data {
		* struct dpu_crtc_mixer: stores the map for each virtual pipeline in the CRTC
		* @hw_lm: LM HW Driver context
		* @lm_ctl: CTL Path HW driver context
		* @encoder: Encoder attached to this lm & ctl
		* @mixer_op_mode: mixer blending operation mode
		* @flush_mask: mixer flush mask for ctl, mixer and pipe
		*/
		struct dpu_crtc_mixer {
		struct dpu_hw_mixer *hw_lm;
		struct dpu_hw_ctl *lm_ctl;
		struct drm_encoder *encoder;
		u32 mixer_op_mode;
		u32 flush_mask;
		};

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