Commit a5f2246f authored by Kamal Dasu's avatar Kamal Dasu Committed by Rob Herring
Browse files

dt: bindings: mtd: replace references to nand.txt with nand-controller.yaml 



nand-controller.yaml replaced nand.txt however the references to it were
not updated. This change updates these references wherever it appears in
bindings documentation.

Fixes: 212e4969 ("dt-bindings: mtd: Add YAML schemas for the generic NAND options")
Signed-off-by: default avatarKamal Dasu <kdasu.kdev@gmail.com>
Signed-off-by: default avatarRob Herring <robh@kernel.org>
parent 8d665693

Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt

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@@ -24,7 +24,7 @@ Optional children nodes: 
Children nodes represent the available nand chips.



Other properties:

see Documentation/devicetree/bindings/mtd/nand.txt for generic bindings.

see Documentation/devicetree/bindings/mtd/nand-controller.yaml for generic bindings.



Example demonstrate on AXG SoC:

Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt

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@@ -101,12 +101,12 @@ Required properties: 
                              number (e.g., 0, 1, 2, etc.)

- #address-cells            : see partition.txt

- #size-cells               : see partition.txt

- nand-ecc-strength         : see nand.txt

- nand-ecc-step-size        : must be 512 or 1024. See nand.txt

- nand-ecc-strength         : see nand-controller.yaml

- nand-ecc-step-size        : must be 512 or 1024. See nand-controller.yaml



Optional properties:

- nand-on-flash-bbt         : boolean, to enable the on-flash BBT for this

                              chip-select. See nand.txt

                              chip-select. See nand-controller.yaml

- brcm,nand-oob-sector-size : integer, to denote the spare area sector size

                              expected for the ECC layout in use. This size, in

                              addition to the strength and step-size,

Documentation/devicetree/bindings/mtd/denali-nand.txt

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@@ -22,16 +22,16 @@ Sub-nodes: 
      select is connected.



  Optional properties:

    - nand-ecc-step-size: see nand.txt for details.

    - nand-ecc-step-size: see nand-controller.yaml for details.

      If present, the value must be

        512        for "altr,socfpga-denali-nand"

        1024       for "socionext,uniphier-denali-nand-v5a"

        1024       for "socionext,uniphier-denali-nand-v5b"

    - nand-ecc-strength: see nand.txt for details. Valid values are:

    - nand-ecc-strength: see nand-controller.yaml for details. Valid values are:

        8, 15      for "altr,socfpga-denali-nand"

        8, 16, 24  for "socionext,uniphier-denali-nand-v5a"

        8, 16      for "socionext,uniphier-denali-nand-v5b"

    - nand-ecc-maximize: see nand.txt for details

    - nand-ecc-maximize: see nand-controller.yaml for details



The chip nodes may optionally contain sub-nodes describing partitions of the

address space. See partition.txt for more detail.

Documentation/devicetree/bindings/mtd/fsmc-nand.txt

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@@ -30,9 +30,9 @@ Optional properties: 
                 command is asserted. Zero means one cycle, 255 means 256

                 cycles.

- bank: default NAND bank to use (0-3 are valid, 0 is the default).

- nand-ecc-mode      : see nand.txt

- nand-ecc-strength  : see nand.txt

- nand-ecc-step-size : see nand.txt

- nand-ecc-mode      : see nand-controller.yaml

- nand-ecc-strength  : see nand-controller.yaml

- nand-ecc-step-size : see nand-controller.yaml



Can support 1-bit HW ECC (default) or if stronger correction is required,

software-based BCH.

Documentation/devicetree/bindings/mtd/gpmc-nand.txt

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@@ -8,7 +8,7 @@ explained in a separate documents - please refer to 
Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt



For NAND specific properties such as ECC modes or bus width, please refer to

Documentation/devicetree/bindings/mtd/nand.txt

Documentation/devicetree/bindings/mtd/nand-controller.yaml





Required properties:

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