Commit a5ebfe12 authored by David S. Miller's avatar David S. Miller
Browse files


Jeff Kirsher says:

====================
1GbE Intel Wired LAN Driver Updates 2020-02-19

This series contains updates to e1000e and igc drivers.

Ben Dooks adds a missing cpu_to_le64() in the e1000e transmit ring flush
function.

Jia-Ju Bai replaces a couple of udelay() with usleep_range() where we
could sleep while holding a spinlock in e1000e.

Chen Zhou make 2 functions static in igc,

Sasha finishes the legacy power management support in igc by adding
resume and schedule suspend requests.  Also added register dump
functionality in the igc driver.  Added device id support for the next
generation of i219 devices in e1000e.  Fixed a typo in the igc driver
that referenced a device that is not support in the driver.  Added the
missing PTP support when suspending now that igc has legacy power
management support.  Added PCIe error detection, slot reset and resume
capability in igc.  Added WoL support for igc as well.  Lastly, added a
code comment to distinguish between interrupt and flag definitions.

Vitaly adds device id support for Tiger Lake platforms, which has
another next generation of i219 device in e1000e.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 5f9721a2 67082b53
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+2 −0
Original line number Diff line number Diff line
@@ -897,6 +897,7 @@ static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data)
	case e1000_pch_cnp:
		/* fall through */
	case e1000_pch_tgp:
	case e1000_pch_adp:
		mask |= BIT(18);
		break;
	default:
@@ -1561,6 +1562,7 @@ static void e1000_loopback_cleanup(struct e1000_adapter *adapter)
	case e1000_pch_spt:
	case e1000_pch_cnp:
	case e1000_pch_tgp:
	case e1000_pch_adp:
		fext_nvm11 = er32(FEXTNVM11);
		fext_nvm11 &= ~E1000_FEXTNVM11_DISABLE_MULR_FIX;
		ew32(FEXTNVM11, fext_nvm11);
+6 −0
Original line number Diff line number Diff line
@@ -97,6 +97,11 @@ struct e1000_hw;
#define E1000_DEV_ID_PCH_TGP_I219_LM14		0x15F9
#define E1000_DEV_ID_PCH_TGP_I219_V14		0x15FA
#define E1000_DEV_ID_PCH_TGP_I219_LM15		0x15F4
#define E1000_DEV_ID_PCH_TGP_I219_V15		0x15F5
#define E1000_DEV_ID_PCH_ADP_I219_LM16		0x1A1E
#define E1000_DEV_ID_PCH_ADP_I219_V16		0x1A1F
#define E1000_DEV_ID_PCH_ADP_I219_LM17		0x1A1C
#define E1000_DEV_ID_PCH_ADP_I219_V17		0x1A1D

#define E1000_REVISION_4	4

@@ -121,6 +126,7 @@ enum e1000_mac_type {
	e1000_pch_spt,
	e1000_pch_cnp,
	e1000_pch_tgp,
	e1000_pch_adp,
};

enum e1000_media_type {
+7 −0
Original line number Diff line number Diff line
@@ -317,6 +317,7 @@ static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
	case e1000_pch_spt:
	case e1000_pch_cnp:
	case e1000_pch_tgp:
	case e1000_pch_adp:
		if (e1000_phy_is_accessible_pchlan(hw))
			break;

@@ -460,6 +461,7 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
		case e1000_pch_spt:
		case e1000_pch_cnp:
		case e1000_pch_tgp:
		case e1000_pch_adp:
			/* In case the PHY needs to be in mdio slow mode,
			 * set slow mode and try to get the PHY id again.
			 */
@@ -703,6 +705,7 @@ static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
	case e1000_pch_spt:
	case e1000_pch_cnp:
	case e1000_pch_tgp:
	case e1000_pch_adp:
	case e1000_pchlan:
		/* check management mode */
		mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
@@ -1642,6 +1645,7 @@ static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
	case e1000_pch_spt:
	case e1000_pch_cnp:
	case e1000_pch_tgp:
	case e1000_pch_adp:
		rc = e1000_init_phy_params_pchlan(hw);
		break;
	default:
@@ -2095,6 +2099,7 @@ static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
	case e1000_pch_spt:
	case e1000_pch_cnp:
	case e1000_pch_tgp:
	case e1000_pch_adp:
		sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
		break;
	default:
@@ -3133,6 +3138,7 @@ static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
	case e1000_pch_spt:
	case e1000_pch_cnp:
	case e1000_pch_tgp:
	case e1000_pch_adp:
		bank1_offset = nvm->flash_bank_size;
		act_offset = E1000_ICH_NVM_SIG_WORD;

@@ -4077,6 +4083,7 @@ static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
	case e1000_pch_spt:
	case e1000_pch_cnp:
	case e1000_pch_tgp:
	case e1000_pch_adp:
		word = NVM_COMPAT;
		valid_csum_mask = NVM_COMPAT_VALID_CSUM;
		break;
+2 −2
Original line number Diff line number Diff line
@@ -1363,7 +1363,7 @@ s32 e1000e_get_hw_semaphore(struct e1000_hw *hw)
		if (!(swsm & E1000_SWSM_SMBI))
			break;

		usleep_range(50, 100);
		udelay(100);
		i++;
	}

@@ -1381,7 +1381,7 @@ s32 e1000e_get_hw_semaphore(struct e1000_hw *hw)
		if (er32(SWSM) & E1000_SWSM_SWESMBI)
			break;

		usleep_range(50, 100);
		udelay(100);
	}

	if (i == timeout) {
+8 −1
Original line number Diff line number Diff line
@@ -3536,6 +3536,7 @@ s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca)
		break;
	case e1000_pch_cnp:
	case e1000_pch_tgp:
	case e1000_pch_adp:
		if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) {
			/* Stable 24MHz frequency */
			incperiod = INCPERIOD_24MHZ;
@@ -3807,7 +3808,7 @@ static void e1000_flush_tx_ring(struct e1000_adapter *adapter)
	tdt = er32(TDT(0));
	BUG_ON(tdt != tx_ring->next_to_use);
	tx_desc =  E1000_TX_DESC(*tx_ring, tx_ring->next_to_use);
	tx_desc->buffer_addr = tx_ring->dma;
	tx_desc->buffer_addr = cpu_to_le64(tx_ring->dma);

	tx_desc->lower.data = cpu_to_le32(txd_lower | size);
	tx_desc->upper.data = 0;
@@ -4049,6 +4050,7 @@ void e1000e_reset(struct e1000_adapter *adapter)
	case e1000_pch_cnp:
		/* fall-through */
	case e1000_pch_tgp:
	case e1000_pch_adp:
		fc->refresh_time = 0xFFFF;
		fc->pause_time = 0xFFFF;

@@ -7757,6 +7759,11 @@ static const struct pci_device_id e1000_pci_tbl[] = {
	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM14), board_pch_cnp },
	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V14), board_pch_cnp },
	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM15), board_pch_cnp },
	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V15), board_pch_cnp },
	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM16), board_pch_cnp },
	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V16), board_pch_cnp },
	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM17), board_pch_cnp },
	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V17), board_pch_cnp },

	{ 0, 0, 0, 0, 0, 0, 0 }	/* terminate list */
};
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