Commit a5df4c14 authored by Andy Shevchenko's avatar Andy Shevchenko Committed by Wolfram Sang
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i2c: designware: Switch header to use BIT() and GENMASK() 



Currently header file uses partially BIT() and GENMASK() macros.
Switch it to use those macros in all cases where it's applicable
for the sake of consistency.

Signed-off-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: default avatarJarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: default avatarWolfram Sang <wsa@kernel.org>
parent 0b01392c

drivers/i2c/busses/i2c-designware-core.h

+46 −46
Original line number Diff line number Diff line
@@ -25,18 +25,18 @@ 
					I2C_FUNC_SMBUS_BLOCK_DATA |	\

					I2C_FUNC_SMBUS_I2C_BLOCK)



#define DW_IC_CON_MASTER		0x1

#define DW_IC_CON_SPEED_STD		0x2

#define DW_IC_CON_SPEED_FAST		0x4

#define DW_IC_CON_SPEED_HIGH		0x6

#define DW_IC_CON_SPEED_MASK		0x6

#define DW_IC_CON_10BITADDR_SLAVE		0x8

#define DW_IC_CON_10BITADDR_MASTER	0x10

#define DW_IC_CON_RESTART_EN		0x20

#define DW_IC_CON_SLAVE_DISABLE		0x40

#define DW_IC_CON_STOP_DET_IFADDRESSED		0x80

#define DW_IC_CON_TX_EMPTY_CTRL		0x100

#define DW_IC_CON_RX_FIFO_FULL_HLD_CTRL		0x200

#define DW_IC_CON_MASTER			BIT(0)

#define DW_IC_CON_SPEED_STD			(1 << 1)

#define DW_IC_CON_SPEED_FAST			(2 << 1)

#define DW_IC_CON_SPEED_HIGH			(3 << 1)

#define DW_IC_CON_SPEED_MASK			GENMASK(2, 1)

#define DW_IC_CON_10BITADDR_SLAVE		BIT(3)

#define DW_IC_CON_10BITADDR_MASTER		BIT(4)

#define DW_IC_CON_RESTART_EN			BIT(5)

#define DW_IC_CON_SLAVE_DISABLE			BIT(6)

#define DW_IC_CON_STOP_DET_IFADDRESSED		BIT(7)

#define DW_IC_CON_TX_EMPTY_CTRL			BIT(8)

#define DW_IC_CON_RX_FIFO_FULL_HLD_CTRL		BIT(9)



/*

 * Registers offset
@@ -81,19 +81,19 @@ 
#define DW_IC_COMP_TYPE		0xfc

#define DW_IC_COMP_TYPE_VALUE	0x44570140



#define DW_IC_INTR_RX_UNDER	0x001

#define DW_IC_INTR_RX_OVER	0x002

#define DW_IC_INTR_RX_FULL	0x004

#define DW_IC_INTR_TX_OVER	0x008

#define DW_IC_INTR_TX_EMPTY	0x010

#define DW_IC_INTR_RD_REQ	0x020

#define DW_IC_INTR_TX_ABRT	0x040

#define DW_IC_INTR_RX_DONE	0x080

#define DW_IC_INTR_ACTIVITY	0x100

#define DW_IC_INTR_STOP_DET	0x200

#define DW_IC_INTR_START_DET	0x400

#define DW_IC_INTR_GEN_CALL	0x800

#define DW_IC_INTR_RESTART_DET	0x1000

#define DW_IC_INTR_RX_UNDER	BIT(0)

#define DW_IC_INTR_RX_OVER	BIT(1)

#define DW_IC_INTR_RX_FULL	BIT(2)

#define DW_IC_INTR_TX_OVER	BIT(3)

#define DW_IC_INTR_TX_EMPTY	BIT(4)

#define DW_IC_INTR_RD_REQ	BIT(5)

#define DW_IC_INTR_TX_ABRT	BIT(6)

#define DW_IC_INTR_RX_DONE	BIT(7)

#define DW_IC_INTR_ACTIVITY	BIT(8)

#define DW_IC_INTR_STOP_DET	BIT(9)

#define DW_IC_INTR_START_DET	BIT(10)

#define DW_IC_INTR_GEN_CALL	BIT(11)

#define DW_IC_INTR_RESTART_DET	BIT(12)



#define DW_IC_INTR_DEFAULT_MASK		(DW_IC_INTR_RX_FULL | \

					 DW_IC_INTR_TX_ABRT | \
@@ -105,13 +105,13 @@ 
					 DW_IC_INTR_RX_UNDER | \

					 DW_IC_INTR_RD_REQ)



#define DW_IC_STATUS_ACTIVITY		0x1

#define DW_IC_STATUS_ACTIVITY		BIT(0)

#define DW_IC_STATUS_TFE		BIT(2)

#define DW_IC_STATUS_MASTER_ACTIVITY	BIT(5)

#define DW_IC_STATUS_SLAVE_ACTIVITY	BIT(6)



#define DW_IC_SDA_HOLD_RX_SHIFT		16

#define DW_IC_SDA_HOLD_RX_MASK		GENMASK(23, DW_IC_SDA_HOLD_RX_SHIFT)

#define DW_IC_SDA_HOLD_RX_MASK		GENMASK(23, 16)



#define DW_IC_ERR_TX_ABRT	0x1
@@ -154,20 +154,20 @@ 
#define ABRT_SLAVE_ARBLOST	14

#define ABRT_SLAVE_RD_INTX	15



#define DW_IC_TX_ABRT_7B_ADDR_NOACK	(1UL << ABRT_7B_ADDR_NOACK)

#define DW_IC_TX_ABRT_10ADDR1_NOACK	(1UL << ABRT_10ADDR1_NOACK)

#define DW_IC_TX_ABRT_10ADDR2_NOACK	(1UL << ABRT_10ADDR2_NOACK)

#define DW_IC_TX_ABRT_TXDATA_NOACK	(1UL << ABRT_TXDATA_NOACK)

#define DW_IC_TX_ABRT_GCALL_NOACK	(1UL << ABRT_GCALL_NOACK)

#define DW_IC_TX_ABRT_GCALL_READ	(1UL << ABRT_GCALL_READ)

#define DW_IC_TX_ABRT_SBYTE_ACKDET	(1UL << ABRT_SBYTE_ACKDET)

#define DW_IC_TX_ABRT_SBYTE_NORSTRT	(1UL << ABRT_SBYTE_NORSTRT)

#define DW_IC_TX_ABRT_10B_RD_NORSTRT	(1UL << ABRT_10B_RD_NORSTRT)

#define DW_IC_TX_ABRT_MASTER_DIS	(1UL << ABRT_MASTER_DIS)

#define DW_IC_TX_ARB_LOST		(1UL << ARB_LOST)

#define DW_IC_RX_ABRT_SLAVE_RD_INTX	(1UL << ABRT_SLAVE_RD_INTX)

#define DW_IC_RX_ABRT_SLAVE_ARBLOST	(1UL << ABRT_SLAVE_ARBLOST)

#define DW_IC_RX_ABRT_SLAVE_FLUSH_TXFIFO	(1UL << ABRT_SLAVE_FLUSH_TXFIFO)

#define DW_IC_TX_ABRT_7B_ADDR_NOACK		BIT(ABRT_7B_ADDR_NOACK)

#define DW_IC_TX_ABRT_10ADDR1_NOACK		BIT(ABRT_10ADDR1_NOACK)

#define DW_IC_TX_ABRT_10ADDR2_NOACK		BIT(ABRT_10ADDR2_NOACK)

#define DW_IC_TX_ABRT_TXDATA_NOACK		BIT(ABRT_TXDATA_NOACK)

#define DW_IC_TX_ABRT_GCALL_NOACK		BIT(ABRT_GCALL_NOACK)

#define DW_IC_TX_ABRT_GCALL_READ		BIT(ABRT_GCALL_READ)

#define DW_IC_TX_ABRT_SBYTE_ACKDET		BIT(ABRT_SBYTE_ACKDET)

#define DW_IC_TX_ABRT_SBYTE_NORSTRT		BIT(ABRT_SBYTE_NORSTRT)

#define DW_IC_TX_ABRT_10B_RD_NORSTRT		BIT(ABRT_10B_RD_NORSTRT)

#define DW_IC_TX_ABRT_MASTER_DIS		BIT(ABRT_MASTER_DIS)

#define DW_IC_TX_ARB_LOST			BIT(ARB_LOST)

#define DW_IC_RX_ABRT_SLAVE_RD_INTX		BIT(ABRT_SLAVE_RD_INTX)

#define DW_IC_RX_ABRT_SLAVE_ARBLOST		BIT(ABRT_SLAVE_ARBLOST)

#define DW_IC_RX_ABRT_SLAVE_FLUSH_TXFIFO	BIT(ABRT_SLAVE_FLUSH_TXFIFO)



#define DW_IC_TX_ABRT_NOACK		(DW_IC_TX_ABRT_7B_ADDR_NOACK | \

					 DW_IC_TX_ABRT_10ADDR1_NOACK | \
@@ -288,12 +288,12 @@ struct dw_i2c_dev { 
	bool			suspended;

};



#define ACCESS_INTR_MASK	0x00000001

#define ACCESS_NO_IRQ_SUSPEND	0x00000002

#define ACCESS_INTR_MASK	BIT(0)

#define ACCESS_NO_IRQ_SUSPEND	BIT(1)



#define MODEL_MSCC_OCELOT	0x00000100

#define MODEL_BAIKAL_BT1	0x00000200

#define MODEL_MASK		0x00000f00

#define MODEL_MSCC_OCELOT	BIT(8)

#define MODEL_BAIKAL_BT1	BIT(9)

#define MODEL_MASK		GENMASK(11, 8)



int i2c_dw_init_regmap(struct dw_i2c_dev *dev);

u32 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset);

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