Commit a5d0f456 authored by Kenneth Feng's avatar Kenneth Feng Committed by Alex Deucher
Browse files

drm/amdgpu: Enable HDP memory light sleep 



Due to the register name and setting change of HDP
memory light sleep on Vega20,change accordingly in
the driver.

Signed-off-by: default avatarKenneth Feng <kenneth.feng@amd.com>
Reviewed-by: default avatarEvan Quan <evan.quan@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a4233cc9

drivers/gpu/drm/amd/amdgpu/soc15.c

+32 −7
Original line number Original line Diff line number Diff line
@@ -65,6 +65,13 @@ 
#define mmMP0_MISC_LIGHT_SLEEP_CTRL                                                             0x01ba

#define mmMP0_MISC_LIGHT_SLEEP_CTRL                                                             0x01ba

#define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX                                                    0

#define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX                                                    0





/* for Vega20 register name change */

#define mmHDP_MEM_POWER_CTRL	0x00d4

#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK	0x00000001L

#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK	0x00000002L

#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK	0x00010000L

#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK		0x00020000L

#define mmHDP_MEM_POWER_CTRL_BASE_IDX	0

/*

/*

 * Indirect registers accessor

 * Indirect registers accessor

 */

 */
@@ -870,6 +877,23 @@ static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable 
{

{

	uint32_t def, data;

	uint32_t def, data;





	if (adev->asic_type == CHIP_VEGA20) {

		def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));



		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))

			data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |

				HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |

				HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |

				HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK;

		else

			data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |

				HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |

				HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |

				HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK);



		if (def != data)

			WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data);

	} else {

		def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));

		def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));





		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))

		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
@@ -880,6 +904,7 @@ static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable 
		if (def != data)

		if (def != data)

			WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);

			WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);

	}

	}

}





static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)

static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)

{

{

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